Article

Statistical Timing Analysis Using Bounds

Authors:

Aseem Agarwal,

David Blaauw,

Vladimir Zolotov,

Sarma VrudhulaAuthors Info & Claims

DATE '03: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Page 10062

Published: 03 March 2003 Publication History

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Abstract

The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing analysis has traditionally suffered from exponential run time complexity with circuit size, due to the dependencies created by reconverging paths in the circuit. In this paper we propose a new approach to statistical timing analysis which uses statistical bounds. First, we provide a formal definition of the statistical delay of a circuit and derive a statistical timing analysis method from this definition. Since this method for finding the exact statistical delay has exponential run time complexity with circuit size, we also propose a new method for computing statistical bounds which has linear run time complexity. We prove the correctness of the proposed bounds. Since we provide both a lower and upper bound on the true statistical delay we can determine the quality of the bounds. The proposed methods were implemented and tested on benchmark circuits. The results demonstrate that the proposed bounds have only a small error.

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Cited By

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Lotze NG�ppert JManoli YDe Micheli GAl-Hashimi BMueller WMacii E(2010)Timing modeling for digital sub-threshold circuitsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1870999(299-302)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1870999
Gulati KKhatri SWakabayashi K(2009)Accelerating statistical static timing analysis using graphics processing unitsProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509705(260-265)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509705
Homma KNitta IShibuya TKyung CChoi KHa S(2008)Non-Gaussian statistical timing models of die-to-die and within-die parameter variations for full chip analysisProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356879(292-297)Online publication date: 21-Jan-2008
https://dl.acm.org/doi/10.5555/1356802.1356879
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Index Terms

Statistical Timing Analysis Using Bounds
1. Hardware
  1. Communication hardware, interfaces and storage
    1. Buses and high-speed links
  2. Very large scale integration design
    1. Application-specific VLSI designs
2. Mathematics of computing
  1. Probability and statistics
    1. Statistical paradigms
      1. Statistical graphics

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Published In

DATE '03: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

March 2003

1112 pages

ISBN:0769518702

Publisher

IEEE Computer Society

United States

Publication History

Published: 03 March 2003

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DATE03

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SIGDA

DATE03: Design, Automation, and Test in Europe 2003

March 3 - 7, 2003

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Lotze NG�ppert JManoli YDe Micheli GAl-Hashimi BMueller WMacii E(2010)Timing modeling for digital sub-threshold circuitsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1870999(299-302)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1870999
Gulati KKhatri SWakabayashi K(2009)Accelerating statistical static timing analysis using graphics processing unitsProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509705(260-265)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509705
Homma KNitta IShibuya TKyung CChoi KHa S(2008)Non-Gaussian statistical timing models of die-to-die and within-die parameter variations for full chip analysisProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356879(292-297)Online publication date: 21-Jan-2008
https://dl.acm.org/doi/10.5555/1356802.1356879
Liu BSciuto D(2008)Signal probability based statistical timing analysisProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403513(562-567)Online publication date: 10-Mar-2008
https://dl.acm.org/doi/10.1145/1403375.1403513
Liu BSciuto D(2008)Spatial correlation extraction via random field simulation and production chip performance regressionProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403502(527-532)Online publication date: 10-Mar-2008
https://dl.acm.org/doi/10.1145/1403375.1403502
Hung WWu XXie YHassoun S(2006)Guaranteeing performance yield in high-level synthesisProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233561(303-309)Online publication date: 5-Nov-2006
https://dl.acm.org/doi/10.1145/1233501.1233561
Kahng ALiu BXu XQu GIsmail YNarayanan VZhou H(2006)Statistical gate delay calculation with crosstalk alignment considerationProceedings of the 16th ACM Great Lakes symposium on VLSI10.1145/1127908.1127961(223-228)Online publication date: 30-Apr-2006
https://dl.acm.org/doi/10.1145/1127908.1127961
Shen BKhatri SZourntos TQu GIsmail YNarayanan VZhou H(2006)Implementation of MOSFET based capacitors for digital applicationsProceedings of the 16th ACM Great Lakes symposium on VLSI10.1145/1127908.1127952(180-186)Online publication date: 30-Apr-2006
https://dl.acm.org/doi/10.1145/1127908.1127952
Ekpanyapong MWaterwai TLim SHirose F(2006)Statistical Bellman-Ford algorithm with an application to retimingProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118514(959-964)Online publication date: 24-Jan-2006
https://dl.acm.org/doi/10.1145/1118299.1118514
Kahng ALiu BXu XHutton MDambre J(2006)Statistical crosstalk aggressor alignment aware interconnect delay calculationProceedings of the 2006 international workshop on System-level interconnect prediction10.1145/1117278.1117297(91-97)Online publication date: 4-Mar-2006
https://dl.acm.org/doi/10.1145/1117278.1117297
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