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ORCIDDSD 2012: Cesme, Izmir, Turkey
- 15th Euromicro Conference on Digital System Design, DSD 2012, Cesme, Izmir, Turkey, September 5-8, 2012. IEEE Computer Society 2012, ISBN 978-1-4673-2498-4
- Halil Kukner, Pieter Weckx, Praveen Raghavan, Ben Kaczer, Francky Catthoor, Liesbet Van der Perre
, Rudy Lauwereins, Guido Groeseneken:
Impact of Duty Factor, Stress Stimuli, and Gate Drive Strength on Gate Delay Degradation with an Atomistic Trap-Based BTI Model. 1-7 - Varadan Savulimedu Veeravalli, Thomas Polzer, Andreas Steininger, Ulrich Schmid:
Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip. 8-17 - Omid Assare, Mahmoud Momtazpour, Maziar Goudarzi:
Accurate Estimation of Leakage Power Variability in Sub-micrometer CMOS Circuits. 18-25 - Kolin Paul, Chinmaya Dash, Mansureh Shahraki Moghaddam:
reMORPH: A Runtime Reconfigurable Architecture. 26-33 - Khalid Latif, Amir-Mohammad Rahmani, Tiberiu Seceleanu, Hannu Tenhunen:
Designing a High Performance and Reliable Networks-on-Chip Using Network Interface Assisted Routing Strategy. 34-41 - David Kramer, Wolfgang Karl:
A Scalable Monitoring Infrastructure for Self-Organizing Many-Core Architectures. 42-49 - Constantinos Efstathiou, Nikolaos Moschopoulos, Kostas Tsoumanis, Kiamal Z. Pekmestzi:
On the Design of Configurable Modulo 2n±1 Residue Generators. 50-56 - Anna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa:
Projected Don't Cares. 57-64 - Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos:
SUT-RNS Residue-to-Binary Converters Design. 65-72 - Roland Dobai, Marcel Baláz, Mária Fischerová:
Automated Generation of Built-In Self-Repair Architectures for Random Logic SoC Cores. 73-78 - Martin Kohlík, Jaroslav Borecký, Hana Kubátová:
Miscellaneous Types of Partial Duplication Modifications for Availability Improvements. 79-83 - Peter Raab, Stefan Krämer, Jürgen Mottok, Stanislav Racek:
Reliability of Task Execution During Safe Software Processing. 84-89 - Dimitris Bekiaris, George Economakos:
Power Optimization Opportunities for a Reconfigurable Arithmetic Component in the Deep Submicron Domain. 90-97 - Eesa Nikahd, Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi:
OWQS: One-Way Quantum Computation Simulator. 98-104 - Christian El Salloum, Martin Elshuber, Oliver Höftberger, Haris Isakovic, Armin Wasicek:
The ACROSS MPSoC - A New Generation of Multi-core Processors Designed for Safety-Critical Embedded Systems. 105-113 - Jürgen Becker, Timo Stripf, Oliver Oey, Michael Hübner, Steven Derrien, Daniel Ménard, Olivier Sentieys, Gerard K. Rauwerda, Kim Sunesen, Nikolaos Kavvadias, Kostas Masselos, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Dimitrios Kritharidis, Nikolaos Mitas, Diana Göhringer:
From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach. 114-121 - Alexander Bochem, Kenneth B. Kent, Rainer Herpers:
FPGA Based Real-Time Tracking Approach with Validation of Precision and Performance. 122-127 - Marcel Dombrowski, Kenneth B. Kent, Yves G. Losier, Adam W. Wilson, Rainer Herpers:
Analyzing Bus Load Data Using an FPGA and a Microcontroller. 128-131 - Andrea Cazzaniga, Gianluca Durelli, Christian Pilato, Donatella Sciuto, Marco D. Santambrogio:
On the Development of a Runtime Reconfigurable Multicore System-on-Chip. 132-135 - Fábio P. Itturriet, Ronaldo Rodrigues Ferreira, Gustavo Girão, Gabriel L. Nazar, Álvaro F. Moreira, Luigi Carro:
Resilient Adaptive Algebraic Architecture for Parallel Detection and Correction of Soft-Errors. 136-139 - Mehmet Kayaalp, Fahrettin Koc, Oguz Ergin:
Improving the Soft Error Resilience of the Register Files Using SRAM Bitcells with Built-In Comparators. 140-143 - Ali Azarpeyvand, Mostafa E. Salehi, Sied Mehdi Fakhraie:
Vulnerability Analysis for Custom Instructions. 144-147 - Farhad Mehdipour, Krishna Chaitanya Nunna, Koji Inoue, Kazuaki J. Murakami:
A Three-Dimensional Integrated Accelerator. 148-151 - Roel Jordans, Rosilde Corvino, Lech Józwiak:
Algorithm Parallelism Estimation for Constraining Instruction-Set Synthesis for VLIW Processors. 152-155 - Zouha Cherif, Jean-Luc Danger, Sylvain Guilley, Lilian Bossuet:
An Easy-to-Design PUF Based on a Single Oscillator: The Loop PUF. 156-162 - Eugen Leontie, Gedare Bloom, Bhagirath Narahari, Rahul Simha:
No Principal Too Small: Memory Access Control for Fine-Grained Protection Domains. 163-170 - Jo Vliegen, Karel Wouters, Christian Grahn, Tobias Pulls:
Hardware Strengthening a Distributed Logging Scheme. 171-176 - Yousra Alkabani:
Trojan Immune Circuits Using Duality. 177-184 - Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser:
Semi-distributed Control for FPGA-based Reconfigurable Systems. 185-192 - Nicolas Celedon, Rodolfo Redlich, Miguel E. Figueroa:
FPGA-based Neural Network for Nonuniformity Correction on Infrared Focal Plane Arrays. 193-200 - Masoumeh Ebrahimi, Masoud Daneshtalab, Juha Plosila, Hannu Tenhunen:
MAFA: Adaptive Fault-Tolerant Routing Algorithm for Networks-on-Chip. 201-207 - Amir-Mohammad Rahmani, Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
Power and Thermal Analysis of Stacked Mesh 3D NoC Using AdaptiveXYZ Routing Algorithm. 208-215 - Lech Józwiak, Menno Lindwer, Rosilde Corvino, Paolo Meloni, Laura Micconi, Jan Madsen, Erkan Diken, Deepak Gangadharan, Roel Jordans, Sebastiano Pomata, Paul Pop, Giuseppe Tuveri, Luigi Raffo:
ASAM: Automatic Architecture Synthesis and Application Mapping. 216-225 - João M. P. Cardoso, Tiago Carvalho, José Gabriel F. Coutinho, Pedro C. Diniz, Zlatko Petrov, Wayne Luk:
Controlling Hardware Synthesis with Aspects. 226-233 - Dionisios N. Pnevmatikatos, Tobias Becker, Andreas Brokalakis, Karel Bruneel, Georgi Gaydadjiev, Wayne Luk, Kyprianos Papadimitriou, Ioannis Papaefstathiou, Oliver Pell, Christian Pilato, M. Robart, Marco D. Santambrogio, Donatella Sciuto, Dirk Stroobandt, Tim Todman:
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration. 234-241 - Syed M. A. H. Jafri, Liang Guang, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Energy-Aware Fault-Tolerant Network-on-Chips for Addressing Multiple Traffic Classes. 242-249 - Jan Kastil, Martin Straka, Lukas Miculka, Zdenek Kotásek:
Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA. 250-257 - Markus Ulbricht, Heinrich Theodor Vierhaus, Tobias Koal:
Activity Migration in M-of-N-Systems by Means of Load-Balancing. 258-263 - Syed Rameez Naqvi, Varadan Savulimedu Veeravalli, Andreas Steininger:
Protecting an Asynchronous NoC against Transient Channel Faults. 264-271 - Josef Strnadel, Frantisek Slimarik:
On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels. 272-279 - Mehmet Kayaalp, Fahrettin Koc, Oguz Ergin:
Exploiting Bus Level and Bit Level Inactivity for Preventing Wire Degradation due to Electromigration. 280-287 - Da He, Wolfgang Mueller:
A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-core Platforms. 288-295 - Meisam Abdollahi, Mohammad Khavari Tavana, Somayyeh Koohi, Shaahin Hessabi:
ONC3: All-Optical NoC Based on Cube-Connected Cycles with Quasi-DOR Algorithm. 296-303 - Abdul Naeem, Axel Jantsch, Zhonghai Lu:
Architecture Support and Comparison of Three Memory Consistency Models in NoC Based Systems. 304-311 - Sandro Bartolini, Paolo Grani:
A Simple On-Chip Optical Interconnection for Improving Performance of Coherency Traffic in CMPs. 312-318 - Sheetal Bhandari, Shaila Subbaraman, Shashank Pujari, Fabio Cancare, Francesco Bruschi, Marco D. Santambrogio, Paolo Roberto Grassi:
High Speed Dynamic Partial Reconfiguration for Real Time Multimedia Signal Processing. 319-326 - Gian Mario Bertolotti, Andrea Cristiani, Remo Lombardi, Nikola B. Serbedzija:
The Seat Adaptation System of REFLECT Project: Implementation of a Biocybernetic Loop in an Automotive Environment. 327-334 - Ioannis Sourdis, Christos Strydis, Christos-Savvas Bouganis, Babak Falsafi, Georgi Nedeltchev Gaydadjiev, Alirad Malek, R. Mariani, Dionisios N. Pnevmatikatos, Dhiraj K. Pradhan, Gerard K. Rauwerda, Kim Sunesen, Stavros Tzilis:
The DeSyRe Project: On-Demand System Reliability. 335-342 - Iakovos Mavroidis, Ioannis Mavroidis, Ioannis Papaefstathiou, Luciano Lavagno, Mihai T. Lazarescu, Eduardo de la Torre, Florian Schäfer:
FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA Kernels. 343-348 - Kim Grüttner, Philipp A. Hartmann, Kai Hylla, Sven Rosinger, Wolfgang Nebel, Fernando Herrera, Eugenio Villar, Carlo Brandolese, William Fornaciari, Gianluca Palermo, Chantal Ykman-Couvreur, Davide Quaglia, Francisco Ferrero, Raúl Valencia:
COMPLEX: COdesign and Power Management in PLatform-Based Design Space EXploration. 349-358 - Bahman Arasteh, Amir Masoud Rahmani, Ali Mansoor, Seyed Ghassem Miremadi:
Using Genetic Algorithm to Identify Soft-Error Derating Blocks of an Application Program. 359-367 - Jan Schmidt, Petr Fiser, Jiri Balcarek:
The Influence of Implementation Technology on Dependability Parameters. 368-373 - Felix Miller, Thomas Wild, Andreas Herkersdorf:
TSV-virtualization for Multi-protocol-Interconnect in 3D-ICs. 374-381 - Radhika Sanjeev Jagtap, Sumeet S. Kumar, Rene van Leuken:
A Methodology for Early Exploration of TSV Placement Topologies in 3D Stacked ICs. 382-388 - Alexandre Chagoya-Garzon, Frédéric Rousseau, Frédéric Pétrot:
Multi-device Driver Synthesis Flow for Heterogeneous Hierarchical Systems. 389-396 - Gorker Alp Malazgirt, Ender Culha, Alper Sen, I. Faik Baskaya, Arda Yurdakul:
A Verifiable High Level Data Path Synthesis Framework. 397-404 - M. Yang, Jinmei Lai, Hongying Xu:
Finite State Machine Synthesis Based on Relay-Based Algorithm. 405-410 - Leonel Sousa, Samuel Antao:
VLSI Reverse Converter for RNS Based on the Moduli Set. 411-414 - Samaneh Talebi, Niloofar Abolghasemi, Ali Jahanian:
EJOP: An Extensible Java Processor with Reasonable Performance/Flexibility Trade-off. 415-418 - Silvia Franchini, Antonio Gentile, Giorgio Vassallo, Filippo Sorbello, Salvatore Vitabile:
A Dual-Core Coprocessor with Native 4D Clifford Algebra Support. 419-422 - Mihai T. Lazarescu, Parinaz Sayyah, Davide Quaglia, Francesco Stefanni:
SystemC Model Generation for Realistic Simulation of Networked Embedded Systems. 423-426 - Raimund Ubar, Sergei Kostin, Jaan Raik:
How to Prove that a Circuit is Fault-Free? 427-430 - Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan:
On Modeling and Evaluation of Logic Circuits under Timing Variations. 431-436 - Carina Schmidt-Knorreck, Daniel Knorreck, Raymond Knopp:
IEEE 802.11p Receiver Design for Software Defined Radio Platforms. 437-444 - Matthias Ihmig, Michael Feilen, Andreas Herkersdorf:
Analytical Design Space Exploration Based on Statistically Refined Runtime and Logic Estimation for Software Defined Radios. 445-452 - Oussama Lazrak, Pierre Leray, Christophe Moy:
HDCRAM Proof-of-Concept for Opportunistic Spectrum Access. 453-458 - Vincent Berg, Dominique Noguet, Xavier Popon:
A Flexible Hardware Platform for Mobile Cognitive Radio Applications. 459-462 - Fabienne Nouvel, Philippe Tanguy:
Flexible OFDM Waveform for PLC/RF In-Vehicle Communications. 463-468 - Davide Bresolin, Luigi Di Guglielmo, Luca Geretti, Riccardo Muradore, Paolo Fiorini, Tiziano Villa:
Open Problems in Verification and Refinement of Autonomous Robotic Systems. 469-476 - Martin Lukasiewycz, Sebastian Steinhorst, Florian Sagstetter, Wanli Chang, Peter Waszecki, Matthias Kauer, Samarjit Chakraborty:
Cyber-Physical Systems Design for Electric Vehicles. 477-484 - Masahiro Fujita:
Simulation-Based Analysis of Cyberphysical Systems. 485-492 - Alberto Casagrande, Carla Piazza:
Model Checking on Hybrid Automata. 493-500 - Raphael Poss, Mike Lankamp, Qiang Yang, Jian Fu, Michiel W. van Tol, Chris R. Jesshope:
Apple-CORE: Microgrids of SVP Cores - Flexible, General-Purpose, Fine-Grained Hardware Concurrency Management. 501-508 - Luciano Lavagno, Mihai T. Lazarescu, Ioannis Papaefstathiou, Andreas Brokalakis, Johan Walters, Bart Kienhuis, Florian Schäfer:
HEAP: A Highly Efficient Adaptive Multi-processor Framework. 509-516 - Paolo Meloni, Giuseppe Tuveri, Luigi Raffo, Emanuele Cannella, Todor P. Stefanov, Onur Derin, Leandro Fiorin, Mariagiovanna Sami:
System Adaptivity and Fault-Tolerance in NoC-based MPSoCs: The MADNESS Project Approach. 517-524 - Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler:
Coverage-Driven Stimuli Generation. 525-528 - Jian Wang, Andreas Karlsson, Joar Sohl, Dake Liu:
Convolutional Decoding on Deep-pipelined SIMD Processor with Flexible Parallel Memory. 529-532 - Somayeh Kashi, Morteza Saheb Zamani:
Hardware Acceleration of STON Algorithm for Comparing 3-D Structure of Proteins. 533-536 - Ruben Cabral, Helena Sarmento:
High Level Modeling and Simulation of a Baseband Processor for the 60 GHz Band. 537-540 - Pablo González de Aledo Marugán, Javier Gonzalez Bayon, Pablo Sánchez Espeso:
A Virtual Platform for Performance Estimation of Many-core Implementations. 541-544 - Baris Ege, Amitabh Das, Santosh Ghosh, Ingrid Verbauwhede:
Differential Scan Attack on AES with X-tolerant and X-masked Test Response Compactor. 545-552 - Sujoy Sinha Roy, Chester Rebeiro, Debdeep Mukhopadhyay:
A Parallel Architecture for Koblitz Curve Scalar Multiplications on FPGA Platforms. 553-559 - Jan Pospisil, Martin Novotný:
Evaluating Cryptanalytical Strength of Lightweight Cipher PRESENT on Reconfigurable Hardware. 560-567 - Marcin Rogawski, Kris Gaj:
A High-Speed Unified Hardware Architecture for AES and the SHA-3 Candidate Grøstl. 568-575 - Sheng Hao Wang, Anup Das, Akash Kumar, Henk Corporaal:
Minimizing Power Consumption of Spatial Division Based Networks-on-Chip Using Multi-path and Frequency Reduction. 576-583 - Selma Saidi, Pranav Tendulkar, Thierry Lepley, Oded Maler:
Optimal 2D Data Partitioning for DMA Transfers on MPSoCs. 584-591 - Timo Schönwald, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel:
Distance-Constrained Force-Directed Process Mapping for MPSoC Architectures. 592-599 - Jaroslav Sykora, Roman Bartosinski, Lukas Kohout, Martin Danek, Petr Honzík:
Reducing Instruction Issue Overheads in Application-Specific Vector Processors. 600-607 - Prashant Agrawal, Kanishk Sugand, Martin Palkovic, Praveen Raghavan, Liesbet Van der Perre, Francky Catthoor:
Partitioning and Assignment Exploration for Multiple Modes of IEEE 802.11n Modem on Heterogeneous MPSoC Platforms. 608-615 - Norbert Druml, Manuel Menghin, Christian Steger, Reinhold Weiss, Andreas Genser, Holger Bock, Josef Haid:
Adaptive Field Strength ScalingL: A Power Optimization Technique for Contactless Reader / Smart Card Systems. 616-623 - Bahareh Pourshirazi, Ali Jahanian:
RF-Interconnect Resource Assignment and Placement Algorithms in Application Specific ICs to Improve Performance and Reduce Routing Congestion. 624-631 - Tiago Dias, Luis Rosario, Nuno Roma, Leonel Sousa:
High Performance Unified Architecture for Forward and Inverse Quantization in H.264/AVC. 632-639 - Erich Wenger, Thomas Baier, Johannes Feichtner:
JAAVR: Introducing the Next Generation of Security-Enabled RFID Tags. 640-647 - George Provelengios, Paris Kitsos, Nicolas Sklavos, Christos Koulamas:
FPGA-based Design Approaches of Keccak Hash Function. 648-653 - Armin Krieg, Johannes Grinschgl, Norbert Druml, Christian Steger, Reinhold Weiss, Holger Bock, Josef Haid:
PROCOMON: An Automatically Generated Predictive Control Signal Monitor. 654-660 - Apostolos P. Fournaris, Odysseas G. Koufopavlou:
CRT RSA Hardware Architecture with Fault and Simple Power Attack Countermeasures. 661-667 - Eric Senn, Daniel Chillet, Olivier Zendra, Cécile Belleudy, Sébastien Bilavarn, Rabie Ben Atitallah, Christian Samoyeau, A. Fritsch:
Open-People: Open Power and Energy Optimization PLatform and Estimator. 668-675 - Alberto Bonanno, Alessandro Sanginario, Marco Crepaldi, Danilo Demarchi:
A Hardware-In-the-Design Methodology for Wireless Sensor Networks Based on Event-Driven Impulse Radio Ultra-Wide Band. 676-683 - Bassem Ouni, Cécile Belleudy, Eric Senn:
Energy Characterization and Classification of Embedded Operating System Services. 684-691 - Fernando Herrera, Hector Posadas, Eugenio Villar, Daniel Calvo:
Enhanced IP-XACT Platform Descriptions for Automatic Generation from UML/MARTE of Fast Performance Models for DSE. 692-699 - H. Gregor Molter, Johannes Kohlmann, Sorin A. Huss:
Automated Generation of Embedded Systems Software from Timed DEVS Model of Computation Specifications. 700-707 - Emad Samuel Malki Ebeid, Davide Quaglia, Franco Fummi:
Generation of VHDL Code from UML/MARTE Sequence Diagrams for Verification and Synthesis. 708-714 - Manel Ammar, Mouna Baklouti, Mohamed Abid:
Extending MARTE to Support the Specification and the Generation of Data Intensive Applications for Massively Parallel SoC. 715-722 - Cameron Patterson, Thomas Preston, Francesco Galluppi, Steve B. Furber:
Managing a Massively-Parallel Resource-Constrained Computing Architecture. 723-726 - Jochem H. Rutgers, Marco Jan Gerrit Bekooij, Gerard J. M. Smit:
Evaluation of a Connectionless NoC for a Real-Time Distributed Shared Memory Many-Core System. 727-730 - Mostafa Moazzen, Akram Reza, Midia Reshadi:
CoolMap: A Thermal-Aware Mapping Algorithm for Application Specific Networks-on-Chip. 731-734 - Hiroki Ito, Mitsuru Shiozaki, Anh-Tuan Hoang, Takeshi Fujino:
Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit. 735-738 - Marcel Steine, Marc Geilen, Twan Basten:
A Distributed Feedback Control Mechanism for Quality-of-Service Maintenance in Wireless Sensor Networks. 739-742 - Olivera Jovanovic, Peter Marwedel, Iuliana Bacivarov, Lothar Thiele:
MAMOT: Memory-Aware Mapping Optimization Tool for MPSoC. 743-750 - Paolo Burgio, Andrea Marongiu, Dominique Heller, Cyrille Chavet, Philippe Coussy, Luca Benini:
OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory Clusters. 751-758 - Yashar Asgarieh, Mohammad Hassan Khabbazian, Mehdi Modarressi, Hamid Sarbazi-Azad:
A Game Theoretical Thermal - Aware Run - Time Task Synchronization Method for Multiprocessor Systems - on - Chip. 759-765 - Cor Meenderinck, Anca Mariana Molnos, Kees Goossens:
Composable Virtual Memory for an Embedded SoC. 766-773 - Rosilde Corvino, Erkan Diken, Abdoulaye Gamatié, Lech Józwiak:
Transformation-Based Exploration of Data Parallel Architecture for Customizable Hardware: A JPEG Encoder Case Study. 774-781 - Mário P. Véstias, Horácio C. Neto:
Parallel Decimal Multipliers and Squarers Using Karatsuba-Ofman's Algorithm. 782-788 - Adam Klimowicz, Valery Salauyou:
The Synthesis of Combined Mealy and Moore Machines Structural Model Using Values of Output Variables as Codes of States. 789-794 - Pedro Miguens Matutino, Héctor Pettenghi, Ricardo Chaves, Leonel Sousa:
RNS Arithmetic Units for Modulo {2^n+-k}. 795-802 - Catalin Bogdan Ciobanu, Georgi Kuzmanov, Georgi Gaydadjiev:
Scalability Study of Polymorphic Register Files. 803-808 - Ali Sentürk, Mustafa Gök:
Pipelined Large Multiplier Designs on FPGAs. 809-814 - Bogdan Spinean, Georgi Gaydadjiev:
Implementation Study of FFT on Multi-lane Vector Processors. 815-822 - Rene Krenz-Baath, Friedrich Hapke, Rolf Hinze, Reinhard Meier, Maija Ryynaenen, Andreas Glowatz:
Robust Evaluation of Weighted Random Logic BIST Structures in Industrial Designs. 823-829 - Satish Kumar Sadasivam, Sangram Alapati, Varun Mallikarjunan:
Test Generation Approach for Post-Silicon Validation of High End Microprocessor. 830-836 - Benaoumeur Senouci, Anne-Johan Annema, Mark J. Bentum, Hans G. Kerkhoff:
Investigating Dependability of Short-Range Wireless Embedded Systems through Hardware Platform Based Design. 837-843 - Christian Gleichner, Heinrich Theodor Vierhaus, Piet Engelke:
Scan Based Tests via Standard Interfaces. 844-851 - Mohammadreza Najafi, Saeed Safari, Zainalabedin Navabi:
Soft Error Analysis on Communication Channels in On-Chip Communication Networks. 852-857 - Álvaro Díaz Suárez, Raul Diego, Pablo Sánchez Espeso:
Virtual Platform for Wireless Sensor Networks. 858-865 - Paolo Roberto Grassi, Donatella Sciuto:
Energy-Aware FPGA-based Architecture for Wireless Sensor Networks. 866-873 - Paolo Roberto Grassi, Vincenzo Rana, Ivan Beretta, Donatella Sciuto:
Tacit Consent: A Technique to Reduce Redundant Transmissions from Spatially Correlated Nodes in Wireless Sensor Networks. 874-881 - Gervin Thomas, Karthik Chandrasekar, Benny Akesson, Ben H. H. Juurlink, Kees Goossens:
A Predictor-Based Power-Saving Policy for DRAM Memories. 882-889 - Nelson V. Silva, Manuel Ventura, Arnaldo S. R. Oliveira, Nuno Borges Carvalho:
Evaluation of an FPGA-based Reconfigurable SoC for All-Digital Flexible RF Transmitters. 890-895 - Fardin Derogarian, João Canas Ferreira, Vítor M. Grade Tavares:
Design and Implementation of a Circuit for Mesh Networks with Application in Body Area Networks. 896-901 - Elias Baaklini, Hassan Sbeity, Smaïl Niar:
H.264 Macroblock Line Level Parallel Video Decoding on Embedded Multicore Processors. 902-906 - Abdulkadir Akin, Elif Erdede, Hossein Afshari, Alexandre Schmid, Yusuf Leblebici:
Enhanced Omnidirectional Image Reconstruction Algorithm and Its Real-Time Hardware. 907-914 - Taoufik Chouta, Jean-Luc Danger, Laurent Sauvage, Tarik Graba:
A Small and High-Performance Coprocessor for Fingerprint Match-on-Card. 915-922 - Mario Donato Marino:
On-Package Scalability of RF and Inductive Memory Controllers. 923-930 - Alessandra Majani, Maria Chiara Lorena, Giovanni Danese, Francesco Leporati:
A Hardware Accelerator for Real Time Simulation of Complex Neuronal Models. 931-937 - Mário P. Véstias, Horácio C. Neto, Helena Sarmento:
Design of High-Speed Viterbi Decoders on Virtex-6 FPGAs. 938-945
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