Abstract
A fully adaptive router with hybrid buffers at the input and output channels was designed, which improves the throughput of its input buffer counterpart by up to 40% and has only 10% higher base latency. An in-depth analysis of different router buffer organization was carried out for a toroidal network, which uses either a deterministic (DOR) or a fully adaptive routing scheme. Each proposal is described in VHDL and evaluated with the Synopsys synthesis tool. Technological restrictions obtained were used to evaluate network performance under both synthetic loads and real applications.
Chapter PDF
References
C. Carrión, R. Beivide, J.A. Gregorio, F. Vallejo, “A flow control mechanism to avoid message deadlock in k-ary n-cube networks,” Fourth International Conference on High Performance Computing, pp. 322–329, India, December,1997.
C. Carrion, R. Beivide, J.A. Gregorio, “Performance Evaluation of Bubble Algorithm: Benefits for k-ary n-cubes. 7th Euromicro on Parallel and Distributed Processing, Madeira, Portugal 1999.
J. Duato, “A necessary and sufficient condition for deadlock-free routing in cut-through and store-and-forward networks”. IEEE Trans. on Parallel and Distributed Systems, vol.7, no.8, pp.841–854, August 1996.
M. Karol, M. Hluchyj, S. Morgan “Input Versus Output Queuing on Space Division Packet Switch”, IEEE Trans. On Communications, vol. COM-35, no. 12, Dec. 1987, pp. 1347–1356.
M. Katevenis, P. Vatsolaki, A. Efthymiou “ Memory Shared Buffer for VLSI Switches”, ACM SIGCOMM, August 1995.
V.S. Pai, P. Ranganathan, S. Adve “Rsim: An execution-Driven Simulator for ILP-Based Shared-Memory Multiprocessors and Uniprocessors”, IEEE TCCA Newsletter, Oct. 1997.
J.M. Prellezo, V. Puente, J.A. Gregorio, R. Beivide, “SICOSYS: a interconnection network simulator for parallel computers,” available at http://www.atc.unican.es/ REPORTS/TR-ATC2-UC98_OnlinePDF.pdf, June 1998.
V. Puente, J.A. Gregorio, J.M. Prellezo, R. Beivide, J. Duato, C. Izu “Adaptive Bubble Router: a Design to Balance Latency and Throughput in Networks for Parallel Computers”, ICPP’99, Sept. 1999.
V. Puente, J.A. Gregorio, C. Izu, R. Beivide, F. Vallejo “Low-level Router Design and its Impact on Supercomputer System Performance”, ICS’99, July 1999.
S.L. Scott, G. Thorson, “The Cray T3E network: Adaptive routing in a high performance 3-D torus”, Hot Interconnects Symposium IV, pp. 147–155, Aug. 1996.
S.C. Woo, M. Ohara, E. Torrie, J.P. Singh, A. Gupta’ The SPLASH-2 Programs: Characterization and Methodological Considerations”. In Proceedings of the 22nd International Symposium on Computer Architecture, pages 24–36. June 1995.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
� 1999 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Puente, V., Gregorio, J.A., Beivide, R., Izu, C. (1999). Impact of the Head-of-Line Blocking on Parallel Computer Networks: Hardware to Applications⋆. In: Amestoy, P., et al. Euro-Par’99 Parallel Processing. Euro-Par 1999. Lecture Notes in Computer Science, vol 1685. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48311-X_173
Download citation
DOI: https://doi.org/10.1007/3-540-48311-X_173
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-66443-7
Online ISBN: 978-3-540-48311-3
eBook Packages: Springer Book Archive