research-article

Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory

Authors:

Luke Dalessandro,

Fran�ois Carouge,

Michael L. Scott,

Michael F. SpearAuthors Info & Claims

ASPLOS XVI: Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems

Pages 39 - 52

https://doi.org/10.1145/1950365.1950373

Published: 05 March 2011 Publication History

Abstract

Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such as Sun's prototype Rock processor and AMD's proposed Advanced Synchronization Facility (ASF), can efficiently execute many transactions, but abort in some cases due to various limitations. Hybrid TM systems can use a compatible software TM (STM) in such cases.

We introduce a family of hybrid TMs built using the recent NOrec STM algorithm that, unlike existing hybrid approaches, provide both low overhead on hardware transactions and concurrent execution of hardware and software transactions. We evaluate implementations for Rock and ASF, exploring how the differing HTM designs affect optimization choices. Our investigation yields valuable input for designers of future best-effort HTMs.

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Honorio BDe Carvalho JMorales CBaldassin AAraujo G(2022)Using Barrier Elision to Improve Transactional Code GenerationACM Transactions on Architecture and Code Optimization10.1145/353331819:3(1-23)Online publication date: 6-Jul-2022
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Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory

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Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory
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Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such as Sun's prototype Rock processor and AMD's proposed Advanced ...
Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory
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cover image ACM Conferences

ASPLOS XVI: Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems

March 2011

432 pages

ISBN:9781450302661

DOI:10.1145/1950365

General Chair:
Rajiv Gupta
University of California, Riverside
,
Program Chair:
Todd C. Mowry
Carnegie Mellon University

ACM SIGARCH Computer Architecture News Volume 39, Issue 1
ASPLOS '11
March 2011
407 pages
ISSN:0163-5964
DOI:10.1145/1961295
Issue’s Table of Contents
ACM SIGPLAN Notices Volume 46, Issue 3
ASPLOS '11
March 2011
407 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/1961296
Issue’s Table of Contents

Copyright © 2011 ACM.

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Published: 05 March 2011

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ASPLOS'11: Sixteenth International Conference on Architectural Support for Programming Languages and Operating Systems

March 5 - 11, 2011

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Cited By

Soni MPal AMiguel J(2022)As-Is Approximate ComputingACM Transactions on Architecture and Code Optimization10.1145/355976120:1(1-26)Online publication date: 17-Nov-2022
https://dl.acm.org/doi/10.1145/3559761
Honorio BDe Carvalho JMorales CBaldassin AAraujo G(2022)Using Barrier Elision to Improve Transactional Code GenerationACM Transactions on Architecture and Code Optimization10.1145/353331819:3(1-23)Online publication date: 6-Jul-2022
https://dl.acm.org/doi/10.1145/3533318
Poudel PSharma G(2021)Adaptive Versioning in Transactional Memory SystemsAlgorithms10.3390/a1406017114:6(171)Online publication date: 31-May-2021
https://doi.org/10.3390/a14060171
Rodriguez MSpear MEmek YCachin C(2020)Brief Announcement: On Implementing Software Transactional Memory in the C++ Memory ModelProceedings of the 39th Symposium on Principles of Distributed Computing10.1145/3382734.3405746(224-226)Online publication date: 31-Jul-2020
https://dl.acm.org/doi/10.1145/3382734.3405746
Alistarh DBrown TSinghal NScheideler CSpear M(2020)Memory Tagging: Minimalist Synchronization for Scalable Concurrent Data StructuresProceedings of the 32nd ACM Symposium on Parallelism in Algorithms and Architectures10.1145/3350755.3400213(37-49)Online publication date: 6-Jul-2020
https://dl.acm.org/doi/10.1145/3350755.3400213
Zardoshti PZhou TBalaji PScott MSpear M(2019)Simplifying Transactional Memory Support in C++ACM Transactions on Architecture and Code Optimization10.1145/332879616:3(1-24)Online publication date: 25-Jul-2019
https://dl.acm.org/doi/10.1145/3328796
Saad MPalmieri RRavindran B(2019)LernaACM Transactions on Storage10.1145/331036815:1(1-24)Online publication date: 22-Mar-2019
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Filipe RIssa SRomano PBarreto JHollingsworth JKeidar I(2019)Stretching the capacity of hardware transactional memory in IBM POWER architecturesProceedings of the 24th Symposium on Principles and Practice of Parallel Programming10.1145/3293883.3295714(107-119)Online publication date: 16-Feb-2019
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Yates RScott MHollingsworth JKeidar I(2019)Leveraging hardware TM in HaskellProceedings of the 24th Symposium on Principles and Practice of Parallel Programming10.1145/3293883.3295711(94-106)Online publication date: 16-Feb-2019
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de Carvalho JAraujo GBaldassin A(2019)The Case for Phase-Based Transactional MemoryIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2018.286171230:2(459-472)Online publication date: 1-Feb-2019
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