May 8, 2017 · Abstract: Technology scaling has continuously improved the density, performance, energy efficiency, and cost of DRAM-based main memory systems.

Abstract—Technology scaling has continuously improved the density, performance, energy efficiency, and cost of DRAM- based main memory systems.

This work identifies that aggressive miniaturization makes DRAM cells more sensitive to random telegraph noise or variable retention time, ...

... First, they utilize static remapping to repair permanent faults, while intermittent faults increase rapidly. Future DRAMs will have bit error ratios as high ...

Technology scaling has continuously improved the density, performance, energy efficiency, and cost of DRAM-based main memory systems.

Dive into the research topics of 'Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices'. Together they form a unique fingerprint.

#013: Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices, Cha et al, HPCA 2017. #014: Reliability-Aware Scheduling on ...

Dec 8, 2023 · Defect Analysis and Cost-effective Resilience Architecture for Future DRAM Devices. In HPCA. 61–72. https://doi.org/10.1109/hpca.2017.30.

In this paper, we present a survey of techniques for improving reliability of DRAM-based main memory. We classify the works based on key parameters.

CiDRA is proposed, a cache-inspired DRAM resilience architecture, which substantially reduces the area and latency overheads of correcting bit errors on ...