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IO connection assignment and RDL routing for flip-chip designs

Authors:

Jin-Tai Yan,

Zhi-Wei ChenAuthors Info & Claims

ASP-DAC '09: Proceedings of the 2009 Asia and South Pacific Design Automation Conference

Pages 588 - 593

Published: 19 January 2009 Publication History

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Abstract

Given a set of IO buffers and bump balls with the capacity constraints between bump balls, an O(n²) IO assignment and RDL routing algorithm is proposed to assign all the IO connections and minimize the total wirelength with satisfying the capacity constraints and guarantee 100% routability if the capacity constraint is permitted, where n is the number of bump balls in a flip-chip design. Compared with the combination of the greedy IO assignment and our RDL routing, our IO assignment reduces the global wirelength by 7.6% after global routing and improves the routability by 8.8% after detailed routing on the average. Compared with the combination of our IO assignment, the single-layer BGA global router[8] and our detailed routing phase, our RDL routing reduces the global wirelength by 15.9% after global routing and improve the routability by 10.6% after detailed routing on the average for some tested circuits in reasonable CPU time.

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Cited By

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Yan J(2016)Performance-Driven Assignment of Buffered I/O Signals in Area-I/O Flip-Chip DesignsACM Transactions on Design Automation of Electronic Systems10.1145/281864221:2(1-24)Online publication date: 28-Jan-2016
https://dl.acm.org/doi/10.1145/2818642
Yan J(2011)IO connection assignment and RDL routing for flip-chip designsACM Transactions on Design Automation of Electronic Systems10.1145/2003695.200370716:4(1-20)Online publication date: 27-Oct-2011
https://dl.acm.org/doi/10.1145/2003695.2003707
Lee HChang YLee PScheffer LPhillips JHu A(2010)Recent research development in flip-chip routingProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133515(404-410)Online publication date: 7-Nov-2010
https://dl.acm.org/doi/10.5555/2133429.2133515

IO connection assignment and RDL routing for flip-chip designs
1. Theory of computation

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Information

Published In

ASP-DAC '09: Proceedings of the 2009 Asia and South Pacific Design Automation Conference

January 2009

902 pages

ISBN:9781424427482

General Chair:
Kazutoshi Wakabayashi
NEC Corporation

Publisher

IEEE Press

Publication History

Published: 19 January 2009

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ASPDAC '09

Sponsor:

SIGDA
IPSJ SIGSLDM
IEICE ESS

ASPDAC '09: Asia and South Pacific Design Automation Conference

January 19 - 22, 2009

Yokohama, Japan

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

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ASPDAC '25

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30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

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Cited By

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Yan J(2016)Performance-Driven Assignment of Buffered I/O Signals in Area-I/O Flip-Chip DesignsACM Transactions on Design Automation of Electronic Systems10.1145/281864221:2(1-24)Online publication date: 28-Jan-2016
https://dl.acm.org/doi/10.1145/2818642
Yan J(2011)IO connection assignment and RDL routing for flip-chip designsACM Transactions on Design Automation of Electronic Systems10.1145/2003695.200370716:4(1-20)Online publication date: 27-Oct-2011
https://dl.acm.org/doi/10.1145/2003695.2003707
Lee HChang YLee PScheffer LPhillips JHu A(2010)Recent research development in flip-chip routingProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133515(404-410)Online publication date: 7-Nov-2010
https://dl.acm.org/doi/10.5555/2133429.2133515

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