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UNION: a unified inter/intra-chip optical network for chip multiprocessors

Published: 17 June 2010 Publication History

Abstract

As modern computing systems become increasingly complex, communication efficiency among and inside chips has become as important as the computation speeds of individual processor cores. Traditionally, inter-chip and intra-chip communication architectures are separately designed to maximize design flexibility under different constraints. However, jointly designing communication architectures for both inter-chip and intra-chip communication could potentially yield better solutions. In this paper, we present a unified inter/intra-chip optical network, called UNION, for chip multiprocessors (CMP). UNION is based on recent progress in nano-photonic technologies. It connects not only processors on a single CMP but also multiple CMPs in a system. UNION employs a hierarchical optical network to separate inter-chip communication traffic from intra-chip communication traffic. It fully utilizes a single optical network to transmit both payload packets and control packets. The network controller on each CMP not only manages intra-chip communications but also collaborate with each other to facilitate inter-chip communications. We compared CMPs using UNION with those using a matched electronic counterpart in 45 nm process. Based on eight applications, simulation results show that on average UNION improves CMP performance by 3.1X while reducing 92% of network energy consumption and 52% of communication delay.

References

[1]
W. Dally and B. Towles, "Route packets, not wires: on-chip interconnection networks," in Design Automation Conference, 2001. Proceedings, 2001, pp. 684--689.
[2]
J. Xu, W. Wolf, J. Henkel, and S. Chakradhar, "A design methodology for application-specific networks-on-chip," ACM Trans. Embed. Comput. Syst., vol. 5, no. 2, pp. 263--280, 2006.
[3]
N. Kirman, M. Kirman, R. K. Dokania, J. F. Martinez, A. B. Apsel, M. A. Watkins, and D. H. Albonesi, "Leveraging optical technology in future bus-based chip multiprocessors," in MICRO 39: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture. Washington, DC, USA: IEEE Computer Society, 2006, pp. 492--503.
[4]
D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. P. Jouppi, M. Fiorentino, A. Davis, N. Binkert, R. G. Beausoleil, and J. H. Ahn, "Corona: System implications of emerging nanophotonic technology," in ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture. Washington, DC, USA: IEEE Computer Society, 2008, pp. 153--164.
[5]
I. O'Connor, F. Mieyeville, F. Gaffiot, A. Scandurra, and G. Nicolescu, "Reduction methods for adapting optical network on chip topologies to specific routing applications," in Proc. Design of Circuits and Integrated Systems (DCIS), November 12--14 2008.
[6]
A. Shacham, K. Bergman, and L. P. Carloni, "Photonic networks-on-chip for future generations of chip multiprocessors," IEEE Trans. Comput., vol. 57, no. 9, pp. 1246--1260, 2008.
[7]
M. J. Cianchetti, J. C. Kerekes, and D. H. Albonesi, "Phastlane: a rapid transit optical routing network," in ISCA, 2009, pp. 441--450.
[8]
K. H. Mo, Y. Ye, X. Wu, W. Zhang, W. Liu, and J. Xu, "A hierarchical hybrid optical-electronic network-on-chip," in IEEE Computer Society Annual Symposium on VLSI, 2010.
[9]
H. Gu, J. Xu, and W. Zhang, "A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip," in DATE, 2009, pp. 3--8.
[10]
D. A. B. Miller, "Physical reasons for optical interconnection," Special Issue on Smart Pixels, International Journal of Opticalelectronics, vol. 11, no. 3, pp. 155--168, 1997.
[11]
G. Van Steenberge, P. Geerinck, S. Van Put, J. Van Koetsem, H. Ottevaere, D. Morlion, H. Thienpont, and P. Van Daele, "MT-compatible laser-ablated interconnections for optical printed circuit boards," Lightwave Technology, Journal of, vol. 22, no. 9, pp. 2083--2090, Sept. 2004.
[12]
S. H. Hwang, M. H. Cho, S.-K. Kang, H.-H. Park, H. S. Cho, S.-H. Kim, K.-U. Shin, and S.-W. Ha, "Passively assembled optical interconnection system based on an optical printed-circuit board," Photonics Technology Letters, IEEE, vol. 18, no. 5, pp. 652--654, 1, 2006.
[13]
A. Apsel, Z. Fu, and A. Andreou, "A 2.5-mw SOS CMOS optical receiver for chip-to-chip interconnect," Lightwave Technology, Journal of, vol. 22, no. 9, pp. 2149--2157, Sept. 2004.
[14]
F. Doany, C. Schow, R. Budd, C. Baks, D. Kuchta, P. Pepeljugoski, J. Kash, F. Libsch, R. Dangel, F. Horst, and B. Offrein, "Chip-to-chip board-level optical data buses," in Optical Fiber communication/National Fiber Optic Engineers Conference, 2008. OFC/NFOEC 2008. Conference on, Feb. 2008, pp. 1--3.
[15]
C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, and K. Asanovic, "Building manycore processor-to-dram networks with monolithic silicon photonics," in HOTI '08: Proceedings of the 2008 16th IEEE Symposium on High Performance Interconnects. Washington, DC, USA: IEEE Computer Society, 2008, pp. 21--30.
[16]
C. G. Requena, F. G. Villam�n, M. E. G�mez, P. L�pez, and J. Duato, "Deterministic versus adaptive routing in fat-trees," in IPDPS. IEEE, 2007, pp. 1--8.
[17]
G. Balamurugan, J. Kennedy, G. Banerjee, J. Jaussi, M. Mansuri, F. O'Mahony, B. Casper, and R. Mooney, "A scalable 5--15 Gbps, 14--75 mw low-power I/O transceiver in 65 nm CMOS," Solid-State Circuits, IEEE Journal of, vol. 43, no. 4, pp. 1010--1019, april 2008.
[18]
J. Poulton, R. Palmer, A. Fuller, T. Greer, J. Eyles, W. Dally, and M. Horowitz, "A 14-mw 6.25-Gb/s transceiver in 90-nm CMOS," Solid-State Circuits, IEEE Journal of, vol. 42, no. 12, pp. 2745--2757, dec. 2007.
[19]
A. Syrbu, A. Mereuta, V. Iakovlev, A. Caliman, P. Royo, and E. Kapon, "10 Gbps VCSELs with high single mode output in 1310nm and 1550 nm wavelength bands," in Optical Fiber communication/National Fiber Optic Engineers Conference, 2008. OFC/NFOEC 2008. Conference on, Feb. 2008, pp. 1--3.
[20]
C. Kromer, G. Sialm, C. Berger, T. Morf, M. Schmatz, F. Ellinger, D. Erni, G.-L. Bona, and H. Jackel, "A 100mw 4 x 10Gb/s transceiver in 80nm CMOS for high-density optical interconnects," in Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International, Feb. 2005, pp. 334--602 Vol. 1.
[21]
G. Masini, G. Capellini, J. Witzens, and C. Gunn, "A 1550nm, 10 Gbps monolithic optical receiver in 130nm CMOS with integrated Ge waveguide photodetector," in Group IV Photonics, 2007 4th IEEE International Conference on, Sept. 2007, pp. 1--3.
[22]
A. W. Poon, F. Xu, and X. Luo, "Cascaded active silicon microresonator array cross-connect circuits for WDM networks-on-chip," in Silicon Photonics III, vol. 6898, no. 1. SPIE, 2008, p. 689812.
[23]
S. Xiao, M. H. Khan, H. Shen, and M. Qi, "Multiple-channel silicon micro-resonator based filters for WDM applications," Opt. Express, vol. 15, no. 12, pp. 7489--7498, 2007.
[24]
F. Xia, L. Sekaric, and Y. Vlasov, "Ultra-compact optical buffers on a silicon chip," Nature Photonics, no. 1, pp. 65--71, Jan. 2007.
[25]
J. K. Doylend and A. P. Knights, "Design and simulation of an integrated fiber-to-chip coupler for silicon-on-insulator waveguides," Selected Topics in Quantum Electronics, IEEE Journal of, vol. 12, no. 6, pp. 1363--1370, Nov.-Dec. 2006.
[26]
G. L. Bona, B. J. Offrein, U. Bapst, C. Berger, R. Beyeler, R. Budd, R. Dangel, L. Dellmann, and F. Horst, "Characterization of parallel optical-interconnect waveguides integrated on a printed circuit board," in Micro-Optics, VCSELs, and Photonic Interconnects, vol. 5453, no. 1. SPIE, 2004, pp. 134--141.

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  • (2017)SWIFTNoCACM Journal on Emerging Technologies in Computing Systems10.1145/306051713:4(1-27)Online publication date: 29-Jun-2017
  • (2016)Dual-mode routing approach for photonic network on chip platformsThe Journal of Supercomputing10.1007/s11227-016-1620-372:3(904-925)Online publication date: 1-Mar-2016
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cover image ACM Conferences
NANOARCH '10: Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
June 2010
90 pages
ISBN:9781424480180

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Published: 17 June 2010

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View all
  • (2018)Scalable Path-Setup Scheme for All-Optical Dynamic Circuit Switched NoCs in Cache Coherent CMPsACM Journal on Emerging Technologies in Computing Systems10.1145/315484014:1(1-27)Online publication date: 8-Mar-2018
  • (2017)SWIFTNoCACM Journal on Emerging Technologies in Computing Systems10.1145/306051713:4(1-27)Online publication date: 29-Jun-2017
  • (2016)Dual-mode routing approach for photonic network on chip platformsThe Journal of Supercomputing10.1007/s11227-016-1620-372:3(904-925)Online publication date: 1-Mar-2016
  • (2015)An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless LinksProceedings of the 9th International Symposium on Networks-on-Chip10.1145/2786572.2786581(1-8)Online publication date: 28-Sep-2015
  • (2015)A hybrid congestion control algorithm for broadcast-based architectures with multiple input queuesThe Journal of Supercomputing10.1007/s11227-015-1384-171:5(1907-1931)Online publication date: 1-May-2015

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