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An architecture-independent approach to FPGA routing based on multi-weighted graphs

Published: 23 September 1994 Publication History
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References

[1]
M. J. ALEXANDER AND G. ROBINS, An Architecture- Independent Unijied Approach to FPGA Routing, Tech. Rep. CS-93-51, Department of Computer Science, University of Virginia, October 1993.
[2]
M. J. ALEXANDER AND G. ROBINS, High-Performance Routing for Field-Programmable Gale Arrays, in Proc. IECEE Intl. ASIC Conf., Rochester, NY, September 1994.
[3]
M. J. ALEXANDER AND G. ROBINS, A New Approach to FPGA Routing Based on Multi- Weighfed Graphs, in Proc. ACM/SIGDA International Workshop on Field- PTOgr anunable Gate Arrays, Berkeley, CA, February 1994.
[4]
T. BARRERA, J. GRIFFITH, S. A. MCKEE, G. ROBINS, AND T. ZHANG, Toward a Steiner Engine: Enhanced Serial and Parallel Implementalions of the Iterated I-Steiner Algorithm, in Proc. Great Lakes Symp. VLSI, Kalamazoo, MI, March 1993, pp. 90-94.
[5]
T. BARRERA, J. GRIFFITH, G. ROBINS, AND T. ZHANG, Narrowing Ihe Gap: Near-Optimal Steiner Trees in Polynomial Time, in Proc. IEEE Intl. ASIC Conf., Rochester, NY, September 1993, pp. 87-90.
[6]
N. B. BHAT AND D. D. HILL, Routable Technology Mapping for LCIT FPGAs, in Proc. IEEE Intl. Conf. Computer-Aided Design, 1992, pp. 95-98.
[7]
S. BROWN, J. ROSE, AND Z. G. VRANESIC, A Detailed Router for Field-Programmable Gate Arrays, IEEE Trans. Computer-Aided Design, 11 (1992), pp. 620-628.
[8]
S. D. BROWN, R. J. FRANCIS, J. ROSE, AND Z. G. VRANESIC, Field-Programmable Gale Arrays, Kluwer Academic Publishers, Boston, MA, 1992.
[9]
P. K. CHAN, M. D. F. SCHLAG, AND J. Y. ZIEN, On Routability Prediction for Field-Programmable Gafe Ar- Taya, in Proc. ACM/IEEE Design Automation Conf., 1993, pp. 326-330.
[10]
K. C. CHEN, J. CONG, Y. DING, A. B. KAHNG, AND P. TRAJMAR, DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimizalion, IEEE Design & Test of Computers, 9 (1992), pp. 7-20.
[11]
J. P. COHOON AND D. S. RICHARDS, Optimal TWO- Terminal a -/3 Wire Routing, Integration: the VLSI JOUP nal, 6 (1988), pp. 35-57.
[12]
W. C. COLLIER AND R. J. WEILAND, Smart Cars, Smart Highways, IEEE Spectrum, 31 (1994), pp. 27-33.
[13]
J. L. GANLEY AND J. P. COHOON, Routing a Multi- Terminal Critical Net: Steiner Tree Construction in the Presence of Obstacles, in Proc. IEEE Intl. Symp. Circuits and Systems, London, England, May 1994, pp. l-.113- 1.116.
[14]
J. L. GANLEY, M. J. GOLIN, AND J. S. SALOWE, Minimum Spanning Trees for Multiply-Weighted Graphs unpublished manuscript, 1994.
[15]
T. GAO, K. C. CHEN, J. CONG, Y. DING, AND C. L. LIU, Placement and Placement Driven Technology Mapping fog FPGA Synthesis, in Proc. IEEE I&l. ASIC Conf., Rochester, NY, September 1993, pp. 87-91.
[16]
M. GAREY AND D. S. JOHNSON, The Rectilinear Steiner Problem is NP-Complete, SIAM J. Applied Math., 32 (1977), pp. 826-834.
[17]
M. HANAN, On Steiner's Problem With Rectilinear Distance, SIAM J. Applied Math., 14 (1966), pp. 255-265.
[18]
T. C. Hu AND T. SHING, The 0-p Routing, in VLSI Circuit Layout: Theory and Design, New York, 1985, IEEE I?ress, pp. 139-143.
[19]
F. K. HWANG, D. S. RICHARDS, AND P. WINTER, The Steiner Tree Problem, North-Holland, 1992.
[20]
A. B. KAHNG AND G. ROBINS, A New Class of her-alive Steiner Tree Heuristics With Good Performance, IEEE Trans. Computer-Aided Design, 11 (1992), pp. 893-902.
[21]
K. KARPLUS, .Ymap: a Technology Mapper for Tablelookup Field-Programmable Gate Arrays, in Proc. ACM/IEEE Design Automation Conf., 1991, pp. 240-243.
[22]
L. Kou, G. MARKOWSKY, AND L. BERMAN, A Fast Algorithm for Steiner Trees, Acta Informatica, 15 (1981), pp. 141-145.
[23]
G. G. LEMIEUX AND S. D. BROWN, A Detailed .Rouling Algorithm for Alloealing Wire Segments in Field- Programmable Gate Arrays, in Proc. ACM/SIGDA Physical Design Workshop, Lake Arrowhead, CA, April 1993.
[24]
F. D. LEWIS AND W. C. PONG, A Negative Reinforcemenl Melhod of PGA Routing, in Proc. ACM/IEEE Design Automation Cord., 1993, pp. 601-605.
[25]
J. ROSE, Parallel Global Routing GOT Standard Cells, IEEE Trans. Computer-Aided Design, 9 (1990), pp. 1085-1095.
[26]
K. ROY, B. GUAN, AND C. SECHEN, FPGA MChi Partitioning and Placement, in Proc. ACM/SIGDA Physical Design Workshop, Lake Arrowhead, CA, April .1993, pp. 211-212.
[27]
M. SCHLAG, J. KONG, AND P. K. CHAN, Routabilily- Driven Technology Mapping for LookUp Table-Based FP- GAS, in Proc. IEEE Kntl. Conf. Computer-Aided Design, 1992, pp. 86-90.
[28]
TRIHBERGER AND M. R. CHENE, Placement-Based Partitioning for Lookup-Table-Based FPGAs, in Proc. IEEE Ml. Conf. Computer-Aided Design, 1992, pp. 91-94.
[29]
S. M. TRIMBERGER, Field-Programmable Gale flrray Technology, S. M. Trimberger, edilo,r, Kluwer Academic Publishers, Boston, MA, 1994.
[30]
B. TSENG, J. ROSE, AND S. BROWN, Improving F.PGA Routing Archileclures Using Architecture and CAL) Interacfions, in Proc. IEEE Intl. Conf. Computer Design, 1992, pp. 99-104.
[31]
Y. F. WV, P. WIDMAYER, AND C. K. WONG, A Faster Approzimalion Algorithm for Ihe Steiner Problem in Graphs, 4cta Informatica, 23 (1986), pp. 223-229.
[32]
XILINX, The Programmable Gate Array Data Book, Xilnx, Inc., San Jose, California, 1993.

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  • (2007)Reconfigurable ComputingundefinedOnline publication date: 2-Nov-2007
  • (2001)Interconnect resource-aware placement for hierarchical FPGAsProceedings of the 2001 IEEE/ACM international conference on Computer-aided design10.5555/603095.603122(132-136)Online publication date: 4-Nov-2001
  • (2001)Interconnect complexity-aware FPGA placement using Rent's ruleProceedings of the 2001 international workshop on System-level interconnect prediction10.1145/368640.368806(115-121)Online publication date: 1-Mar-2001
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cover image ACM Conferences
EURO-DAC '94: Proceedings of the conference on European design automation
September 1994
697 pages
ISBN:0897916859

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Published: 23 September 1994

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September 19 - 23, 1994
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Cited By

View all
  • (2007)Reconfigurable ComputingundefinedOnline publication date: 2-Nov-2007
  • (2001)Interconnect resource-aware placement for hierarchical FPGAsProceedings of the 2001 IEEE/ACM international conference on Computer-aided design10.5555/603095.603122(132-136)Online publication date: 4-Nov-2001
  • (2001)Interconnect complexity-aware FPGA placement using Rent's ruleProceedings of the 2001 international workshop on System-level interconnect prediction10.1145/368640.368806(115-121)Online publication date: 1-Mar-2001
  • (1997)FPGA routing and routability estimation via Boolean satisfiabilityProceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays10.1145/258305.258322(119-125)Online publication date: 9-Feb-1997
  • (1995)New performance-driven FPGA routing algorithmsProceedings of the 32nd annual ACM/IEEE Design Automation Conference10.1145/217474.217589(562-567)Online publication date: 1-Jan-1995

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