research-article

Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths

Authors:

Matthias Sauer,

Tobias Schubert,

Bernd BeckerAuthors Info & Claims

DATE '13: Proceedings of the Conference on Design, Automation and Test in Europe

Pages 448 - 453

Published: 18 March 2013 Publication History

Abstract

Comprehensive coverage of small-delay faults under massive process variations is achieved when multiple paths through the fault locations are sensitized by the test pair set. Using one test pair per path may lead to impractical test set sizes and test application times due to the large number of near-critical paths in state-of-the-art circuits.

We present a novel SAT-based dynamic test-pattern compaction and relaxation method for sensitized paths in sequential and combinational circuits. The method identifies necessary assignments for path sensitization and encodes them as a SAT-instance. An efficient implementation of a bitonic sorting network is used to find test patterns maximizing the number of simultaneously sensitized paths. The compaction is combined with an efficient lifting-based relaxation technique. An innovative implication-based path-conflict analysis is used for a fast identification of conflicting paths.

Detailed experimental results demonstrate the applicability and quality of the method for academical and industrial benchmark circuits. Compared to fault dropping the number of patterns is significantly reduced by over 85% on average while at the same time leaving more than 70% of the inputs unspecified.

References

[1]

R. Sankaralingam, R. Oruganti and N. Touba, "Static Compaction Techniques to Control Scan Vector Power Dissipation," in VLSI Test Symposium, 2000. Proceedings. 18th IEEE, pp. 35--40, 2000.

Digital Library

[2]

I. Pomeranz and S. Reddy, "On Static Compaction of Test Sequences for Synchronous Sequential Circuits," in Proceedings of the 33rd annual Design Automation Conference, DAC '96, pp. 215--220, 1996.

Digital Library

[3]

I. Pomeranz, L. Reddy and S. Reddy, "COMPACTEST: A Method to Generate Compact Test Sets for Combinational Circuits," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 12, pp. 1040--1049, jul 1993.

Digital Library

[4]

E. Rudnick and J. Patel, "Efficient Techniques for Dynamic Test Sequence Compaction," Computers, IEEE Transactions on, vol. 48, no. 3, pp. 323--330, 1999.

Digital Library

[5]

I. Pomeranz and S. Reddy, "Forward-Looking Fault Simulation for Improved Static Compaction," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 20, no. 10, pp. 1262--1265, 2001.

Digital Library

[6]

A. Czutro, I. Polian, P. Engelke, S. Reddy and B. Becker, "Dynamic Compaction in SAT-Based ATPG," in Asian Test Symposium, 2009. ATS '09., pp. 187--190, 2009.

Digital Library

[7]

S. Eggersgluss, R. Krenz-Baath, A. Glowatz, F. Hapke and R. Drechsler, "A New SAT-based ATPG for Generating Highly Compacted Test Sets," in Design and Diagnostics of Electronic Circuits Systems (DDECS), IEEE International Symposium on, pp. 230--235, 2012.

[8]

A. Biere, M. J. H. Heule, H. van Maaren and T. Walsh, eds., Handbook of Satisfiability, vol. 185 of Frontiers in Artificial Intelligence and Applications. IOS Press, February 2009.

Digital Library

[9]

Z. Wang and D. Walker, "Dynamic Compaction for High Quality Delay Test," in VTS 2008, pp. 243--248, 2008.

Digital Library

[10]

J. Saxena and D. Pradhan, "A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits," in Test Conference, 1993. Proceedings., International, pp. 724--733, 1993.

Digital Library

[11]

M. Fukunaga, S. Kajihara, X. Wen, T. Maeda, S. Hamada and Y. Sato, "A Dynamic Test Compaction Procedure for High-quality Path Delay Testing," in Design Automation, 2006. Asia and South Pacific, Conference on, p. 6 pp., 2006.

Digital Library

[12]

B. Koenemann, "LFSR-Coded Test Patterns for Scan Designs," pp. 237--242, 1991.

[13]

F. Hsu, K. Butler and J. Patel, "A Case Study on the Implementation of the Illinois Scan Architecture," in Test Conference, 2001. Proceedings. International, pp. 538--547, 2001.

Digital Library

[14]

J. Rajski, J. Tyszer, M. Kassab and N. Mukherjee, "Embedded Deterministic Test," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, no. 5, pp. 776--792, 2004.

Digital Library

[15]

P. F. Flores, H. C. Neto and J.a.P. Marques-Silva, "An exact solution to the minimum size test pattern problem," ACM Trans. Des. Autom. Electron. Syst., vol. 6, no. 4, pp. 629--644, 2001.

Digital Library

[16]

I. Pomeranz, "Computing Two-Pattern Test Cubes for Transition Path Delay Faults," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. PP, no. 99, pp. 1--11, 2012.

Digital Library

[17]

G. S. Tseitin, "On the Complexity of Derivations in Propositional Calculus," in Studies in Constructive Mathematics and Mathematical Logics (A. Slisenko, ed.), 1968.

[18]

M. Davis, G. Logemann and D. Loveland, "A Machine Program for Theorem Proving," Communications of the ACM, vol. 5, pp. 394--397, 1962.

Digital Library

[19]

W. Qiu, J. Wang, D. Walker, D. Reddy, X. Lu, Z. Li, W. Shi and H. Balachandran, "K longest paths per gate (KLPG) test generation for scan-based sequential circuits," in Test Conference, 2004. Proceedings. ITC 2004. International, pp. 223--231, 2004.

Digital Library

[20]

Z. He, T. Lv, H. Li and X. Li, "An Efficient Algorithm for Finding a Universal Set of Testable Long Paths," in Test Symposium (ATS), 2010 19th IEEE Asian, pp. 319--324, 2010.

Digital Library

[21]

N. K. Jha and S. K. Gupta, Testing of Digital Systems. Cambridge University Press, 2003.

Digital Library

[22]

S. Reddy, Models in Hardware Testing, ch. 3. Springer, 2010.

[23]

K. E. Batcher, "Sorting networks and their applications," in Proceedings of the April 30--May 2, 1968, spring joint computer conference, AFIPS '68 (Spring), pp. 307--314, 1968.

Digital Library

[24]

K. Ravi and F. Somenzi, "Minimal assignments for bounded model checking," in Tools and Algorithms for the Construction and Analysis of Systems, vol. 2988, pp. 31--45, Springer, 2004.

[25]

M. Sauer, S. Reimer, I. Polian, T. Schubert and B. Becker, "Provably Optimal Test Cube Generation using Quantified Boolean Formula Solving," in Design Automation, 2013. Asia and South Pacific, Conference on, 2013.

[26]

T. Schubert, M. Lewis and B. Becker, "antom --- Solver Description," in SAT Race, 2010.

[27]

M. Sauer, A. Czutro, T. Schubert, S. Hillebrecht, I. Polian and B. Becker, "SAT-based Analysis of Sensitisable Paths," in IEEE Design and Diagnostics of Electronic Circuits and Systems, pp. 93--98, April 2011.

[28]

M. Sauer, J. Jiang, A. Czutro, I. Polian and B. Becker, "Efficient SAT-Based Search for Longest Sensitisable Paths," in Asian Test Symp., November 2011.

Digital Library

[29]

I. Hamzaoglu and J. Patel, "Compact Two-Pattern Test Set Generation for Combinational and Full Scan Circuits," in Test Conference, 1998. Proceedings., International, pp. 944--953, 1998.

Digital Library

Cited By

Sauer MRaiola PFeiten LBecker BR�hrmair UPolian I(2017)Sensitized path PUFProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130545(680-685)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130545
Eggersgl�� SWille RDrechsler RHenkel J(2013)Improved SAT-based ATPGProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561847(85-90)Online publication date: 18-Nov-2013
https://dl.acm.org/doi/10.5555/2561828.2561847

Index Terms

Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Hardware validation

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Information

Published In

cover image ACM Conferences

DATE '13: Proceedings of the Conference on Design, Automation and Test in Europe

March 2013

1944 pages

ISBN:9781450321532

General Chair:
Enrico Macii
Politecnico di Torino, IT

Sponsors

EDAA: European Design Automation Association
ECSI
EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE CEDA
The Russian Academy of Sciences: The Russian Academy of Sciences

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EDA Consortium

San Jose, CA, United States

Publication History

Published: 18 March 2013

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DATE 13

Sponsor:

EDAA
EDAC
SIGDA
The Russian Academy of Sciences

DATE 13: Design, Automation and Test in Europe

March 18 - 22, 2013

Grenoble, France

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

Sauer MRaiola PFeiten LBecker BR�hrmair UPolian I(2017)Sensitized path PUFProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130545(680-685)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130545
Eggersgl�� SWille RDrechsler RHenkel J(2013)Improved SAT-based ATPGProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561847(85-90)Online publication date: 18-Nov-2013
https://dl.acm.org/doi/10.5555/2561828.2561847

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