Accelerating functional timing analysis with encoding duplication removal and redundant state propagation
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- Accelerating functional timing analysis with encoding duplication removal and redundant state propagation
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Accelerating functional timing analysis with encoding duplication removal and redundant state propagation
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)Functional timing analysis (FTA) emerges for better timing closure than static timing analysis (STA) by providing the true delay of the circuit as well as its input pattern. For Satisfiability(SAT)-based FTA, a search problem for circuit delay can be ...
Covered Clauses Are Not Propagation Redundant
Automated ReasoningAbstractPropositional proof systems based on recently-developed redundancy properties admit short refutations for many formulas traditionally considered hard. Redundancy properties are also used by procedures which simplify formulas in conjunctive normal ...
Fully redundant decimal addition and subtraction using stored-unibit encoding
Decimal computer arithmetic is experiencing a revived popularity, and there is quest for high-performance decimal hardware units. Successful experiences on binary computer arithmetic may find grounds in decimal arithmetic. For example, the traditional ...
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- CEDA: Council on Electronic Design Automation
- SIGDA: ACM Special Interest Group on Design Automation
- IEEE-CAS: Circuits & Systems
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- IEEE-EDS: Electronic Devices Society
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IEEE Press
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