DAC

A prototype version of a new switch-level fault simulator for digital MOS IC's is described. The simulation program, which is called CSASIM, analyzes CSA (connector-switch-attenuator) circuit models using multiple logic values. A novel method of signal ...

This paper describes the second generation MOTIS mixed-mode simulator. In particular, it extends the current modeling capabilities to include resistors, floating capacitors, and bidirectional transmission gates. It employs a relaxation algorithm with ...

STAtistical Fault ANalysis (STAFAN) is proposed as an alternative to fault simulation of digital circuits. In this analysis, controllabilities and observabilities of circuit nodes are defined as probabilities which are estimated from signal statistics ...

A new logic simulator called THEMIS^TM Logic Simulator for the design of LSI, VLSI and PCBs is described. THEMIS supports design verification and test development from initial specification in behavioral and RTL languages to analysis of the final layout ...

A channel model for routing double-layer cell arrays is presented. A switch-box is defined as an overlapping area of a horizontal channel and a vertical channel. Along the sides of switch-boxes, dynamic terminals are generated by the loose router and ...

In the LSI chip layout design, channel routing is one of the key problems. The problem is to route a specified net list between two rows of terminals across a two layer channel.

This paper presents a new routing algorithm, which is an improved version ...

An algorithm is presented which accomplishes the global routing for a building block or general cell routing problem. A line search technique is employed and therefore no grid is assumed either for the module placements or the pin locations. Instead of ...

The router described in this paper is part of a complete CAD system which aims at hierarchical designs of customized VLSI MOS circuits. It routes global signals as symbolic interconnect and is guaranteed to complete all routing in one pass. The router ...

In this paper, a new hardware description language -HARPA- is presented which was specially designed to permit the description of hierarchically structured digital systems at different levels of abstraction. The system building modules can be ...

The Algorithmic Design Language (ADL), provides a means to procedurally describe the functional, circuit, schematic and mask aspects of integrated circuits. The constructs of this language have been coded in the C language and are intended for ...

This paper describes a new diagrammatic hardware description language SFDL (Symbolic Functional Description Language) and a hierarchical logic design supporting system LDSS (Logic Design Supporting System).

SFDL has three features that help designers ...

The Block Description Language (BDL), a language for capturing the structure of an electronic system, is described. The structure of a system may be specified hierarchically in this language. Additional information may be associated with the structural ...

A layout generator for technology independent implementation of the MOS multiplier is described. The modified Booth's algorithm with a structured floor plan has been used. The layout has been optimized and described as a program in a high level layout ...

A symbolic circuit design language for describing the topology and topography of a VLSI design in a simple and hierarchical manner is described. The language was intended to provide a simple manner of structuring a VLSI design, based on the Mead and ...

This paper describes a cell compiler that translates cell descriptions given in form of Boolean equations including pass transistors into layout descriptions in Caltech Intermediate Form (CIF). The translation process is constrained by given height and ...

In recent years many researchers have tried to apply the traditional database systems to design applications. To date, most of these experiments have been largely unsuccessful. Insufficient computing power may be one reason for this failure. However, ...

An important use for a database management system is in the storage and handling of information for engineering design, particularly integrated circuit design. However, most discussions on this topic have concentrated on the layout of shapes necessary ...

This paper describes a compactor that is practical for compacting whole chips that are designed hierarchically, and can produce a reasonable result in spite of the layout being over-constrained. The layout produced is good enough to be used in high ...

A chip layout procedure for optimizing the performance of critical timing paths in a synchronous digital circuit is presented. The procedure uses the path analysis data produced by a static timing analysis program to generate weights for critical nets ...

This paper describes an interactive router for compacting building block VLSI layout. It allows the designer to manipulate the functional block location on the CRT display without breaking interconnections between functional blocks. Following the ...

This paper gives an overview of expert systems and logic programming as applied to Computer-Aided Design (CAD) systems. Our objective is to show the relevance of these two approaches developed from research in artificial intelligence for the solution of ...

Magic is a “smart” layout system for integrated circuits. The user interface is based on a new design style called logs, which combines the efficiency of mask-level design with the flexibility of symbolic design. The system incorporates expertise about ...

The Magic VLSI layout editor contains an incremental design-rule checker. When the circuit is changed, only the modified areas are rechecked. The checker runs continuously in background to keep information about design-rule violations up-to-date. This ...

The Magic layout editor provides a new operation called plowing, for stretching and compacting Manhattan VLSI layouts. Plowing works directly on the mask-level representation of a layout, allowing portions of it to be rearranged while preserving ...

Detour is the channel router used by the Magic layout system. Based on Rivest and Fiduccia's “greedy” channel router, Detour is capable of routing switchboxes and channels containing obstacles such as preexisting wiring. It jogs nets around multi-layer ...

A new automatic test generation approach for LSI circuits has been presented in the companion papers [1,2]. In this paper we generate tests for a typical LSI circuit using the new approach. The goal of this study is to gain insight into the problems ...

In this paper, we describe functional testing techniques for detecting single stuck-at faults in a microprocessor. These techniques appear to be practical in that a relatively small number of machine language instructions is needed in the programs which ...