A Direct Conversion Receiver Adopting Balanced Three-Phase Analog System

Takafumi YAMAJI
Takeshi UENO
Tetsuro ITAKURA

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E93-A    No.2    pp.367-374
Publication Date: 2010/02/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E93.A.367
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
balanced 3-phase system,  direct conversion receiver,  ΔΣADC,  

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Summary: 
Recent advanced technology makes digital circuits small and the number of digital functional blocks that can be integrated on a single chip is increasing rapidly. On the other hand, reduction in the size of analog circuits has been insufficient. This means that the analog circuit area is relatively large, and reducing analog circuit area can be effective to make a low cost radio receiver. In this paper, a new wireless receiver architecture that occupies small analog area is proposed, and measured results of the core analog blocks are described. To reduce the analog area, a balanced 3-phase analog system is adopted and the functions of analog baseband filters and VGAs are moved to the digital domain. The test chip consists of a 3-phase downconverter and a 3-phase ADC. There is no analog baseband filter on the chip and the analog filter is assumed to be replaced with a digital filter. The downconverter and ADC occupy 0.28 mm2. The measured results show the possibility that the requirements for IMT-2000 are fulfilled even with a small chip area.

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