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ORCIDETS 2012: Annecy, France
- 17th IEEE European Test Symposium, ETS 2012, Annecy, France, May 28 - June 1 2012. IEEE Computer Society 2012, ISBN 978-1-4673-0697-3
- Xiaoqing Wen:
Power-aware testing: The next stage. 1 - Samah Mohamed Saeed, Ozgur Sinanoglu
:
DfT support for launch and capture power reduction in launch-off-capture testing. 1-6 - Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni:
Cost and power efficient timing error tolerance in flip-flop based microprocessor cores. 1-6 - Jakub Janicki, Jerzy Tyszer, Grzegorz Mrugalski, Janusz Rajski:
Bandwidth-aware test compression logic for SoC designs. 1-6 - Paolo Bernardi, Lyl M. Ciganda, Mauricio de Carvalho, Michelangelo Grosso, Jorge Luis Lagos-Benites, Ernesto Sánchez, Matteo Sonza Reorda, Oscar Ballan:
On-line software-based self-test of the Address Calculation Unit in RISC processors. 1-6 - Gabriel L. Nazar, Luigi Carro:
Fast error detection through efficient use of hardwired resources in FPGAs. 1-6 - Cristiana Bolchini, Antonio Miele, Chiara Sandionigi:
Increasing autonomous fault-tolerant FPGA-based systems' lifetime. 1-6 - Mihalis Psarakis, Andreas Apostolakis:
Fault tolerant FPGA processor based on runtime reconfigurable modules. 1-6 - Cândido Duarte, Henrique Cavadas, Pedro Coke, Luis Malheiro, Vítor Grade Tavares, Pedro Guedes de Oliveira:
BIST design for analog cell matching. 1-6 - Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet, Christophe Forel:
Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs. 1-6 - Ender Yilmaz, Sule Ozev:
Adaptive multi-site testing for analog/mixed-signal circuits incorporating neighborhood information. 1-6 - Armin Krieg, Johannes Grinschgl, Christian Steger, Reinhold Weiss, Andreas Genser, Holger Bock, Josef Haid:
Characterization and handling of low-cost micro-architectural signatures in MPSoCs. 1-6 - Fabian Oboril, Mehdi Baradaran Tahoori:
Reducing wearout in embedded processors using proactive fine-grain dynamic runtime adaptation. 1-6 - Manuel J. Barragan Asian, Gildas Léger, José L. Huertas:
OBT for settling error test of sampled-data systems using signal-dependent clocking. 1-6 - Abhishek Jain, Andrea Veggetti, Dennis Crippa, Pierluigi Rolandi:
On-chip delay measurement circuit. 1-6 - Irith Pomeranz:
On the detection of path delay faults by functional broadside tests. 1-6 - Mahesh Prabhu, Jacob A. Abraham:
Functional test generation for hard to detect stuck-at faults using RTL model checking. 1-6 - Stefan Hillebrecht, Michael A. Kochte, Hans-Joachim Wunderlich, Bernd Becker:
Exact stuck-at fault classification in presence of unknowns. 1-6 - Valentin Gherman, Samuel Evain, Yannick Bonhomme:
Memory reliability improvements based on maximized error-correcting codes. 1-6 - Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji:
Time-division multiplexing for testing SoCs with DVS and multiple voltage islands. 1-6 - Urmas Repinski, Hanno Hantson, Maksim Jenihhin, Jaan Raik, Raimund Ubar, Giuseppe Di Guglielmo, Graziano Pravadelli, Franco Fummi:
Combining dynamic slicing and mutation operators for ESL correction. 1-6 - Mohamed Tagelsir Mohammadat, Noohul Basheer Zain Ali, Fawnizu Azmadi Hussin:
Multi-voltage aware resistive open fault modeling. 1-6 - Jae Wook Lee, Ji Hwan (Paul) Chun, Jacob A. Abraham:
Indirect method for random jitter measurement on SoCs using critical path characterization. 1-6 - Chandra K. H. Suresh, Ozgur Sinanoglu, Sule Ozev:
Adaptive testing of chips with varying distributions of unknown response bits. 1-6 - Abishek Ramdas, Ozgur Sinanoglu:
Toggle-masking scheme for x-filtering. 1-6 - Alejandro Cook, Sybille Hellebrand, Hans-Joachim Wunderlich:
Built-in self-diagnosis exploiting strong diagnostic windows in mixed-mode test. 1-6 - Alexander Czutro, Matthias Sauer, Ilia Polian, Bernd Becker:
Multi-conditional SAT-ATPG for power-droop testing. 1-6 - Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian:
On the quality of test vectors for post-silicon characterization. 1-6 - Nadereh Hatami, Rafal Baranowski, Paolo Prinetto, Hans-Joachim Wunderlich:
Efficient system-level aging prediction. 1-6 - Zhaobo Zhang, Xinli Gu, Yaohui Xie, Zhiyuan Wang, Zhanglei Wang, Krishnendu Chakrabarty:
Diagnostic system based on support-vector machines for board-level functional diagnosis. 1-6 - Chih-Sheng Hou, Jin-Fu Li:
Disturbance fault testing on various NAND flash memories. 1 - Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan:
Functional analysis of circuits under timing variations. 1 - Vasilis F. Pavlidis, Hu Xu, Giovanni De Micheli:
Enhanced wafer matching heuristics for 3-D ICs. 1 - Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
Defect analysis in power mode control logic of low-power SRAMs. 1 - Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay:
Coupling-based resistive-open defects in TAS-MRAM architectures. 1 - Yukiya Miura, Yasuo Sato, Yousuke Miyake, Seiji Kajihara:
On-chip temperature and voltage measurement for field testing. 1 - Zhengliang Lv, Linda Milor, Shiyuan Yang:
Impact of NBTI on analog components. 1 - Carolina Metzler, Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel:
Through-Silicon-Via resistive-open defect analysis. 1 - Aritra Banerjee, Shyam Kumar Devarakond, Shreyas Sen, Debashis Banerjee, Abhijit Chatterjee:
Testing of digitally assisted adaptive analog/RF systems using tuning knob - Performance space estimation. 1 - Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
On-chip test comparison for protecting confidential data in secure ICs. 1 - Fábio P. Itturriet, Ronaldo Rodrigues Ferreira, Luigi Carro:
Fault-Tolerant Algebraic Architecture for radiation induced soft-errors. 1 - Syed Zafar Shazli, Mehdi Baradaran Tahoori:
Online detection and recovery of transient errors in front-end structures of microprocessors. 1 - Q. Wang, Andreas Wallin, Viacheslav Izosimov, Urban Ingelsson, Zebo Peng:
Test tool qualification through fault injection. 1 - George Theodorou, Serafeim Chatzopoulos, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos:
A Software-Based Self-Test methodology for on-line testing of data TLBs. 1 - Artur Jutman, Sergei Devadze, Igor Aleksejev, Thomas Wenzel:
Embedded synthetic instruments for Board-Level testing. 1 - Ender Yilmaz, Sule Ozev, Ozgur Sinanoglu, Peter C. Maxwell:
Adaptive testing: Conquering process variations. 1-6 - Friedrich Hapke, Jürgen Schlöffel:
Introduction to the defect-oriented cell-aware test methodology for significant reduction of DPPM rates. 1-6 - Said Hamdioui, Rob Aitken:
VLSI Test technology: Why is the field not sexy enough? 1 - Riccardo Mariani:
The impact of functional safety standards in the design and test of reliable and available integrated circuits. 1 - Xinli Gu, Jeff Rearick, Bill Eklow, Martin Keim, Jun Qian, Artur Jutman, Krishnendu Chakrabarty, Erik Larsson:
Re-using chip level DFT at board level. 1 - Piet Engelke, Hermann Obermeir:
Funding project DIANA - Integrated diagnostics for the analysis of electronic failures in vehicles. 1 - Mohamed Azimane:
Reducing test cost for mixed signal circuits "From TOETS to ELESIS". 1 - Jaan Raik:
FP7 collaborative research project DIAMOND: Diagnosis, error modeling and correction for reliable systems design. 1 - Jörg Henkel, Oliver Bringmann, Andreas Herkersdorf, Wolfgang Rosenstiel, Norbert Wehn:
Dependable embedded systems: The German research foundation DFG priority program SPP 1500. 1 - Marco Ottavi:
Introducing MEDIAN: A new COST Action on manufacturable and dependable multicore architectures at nanoscale. 1 - Shaji Krishnan, Hans G. Kerkhoff:
A robust metric for screening outliers from analogue product manufacturing tests responses. 1-6
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