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Samuel Riedel
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2020 – today
- 2024
- [j4]Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel, Alessandro Ottaviano, Andreas Kurth, Torsten Hoefler, Luca Benini:
A High-Performance, Energy-Efficient Modular DMA Engine Architecture. IEEE Trans. Computers 73(1): 263-277 (2024) - [j3]Nesara Eranna Bethur, Anthony Agnesina, Moritz Brunion, Alberto García Ortiz, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Matheus A. Cavalcante, Samuel Riedel, Luca Benini, Sung Kyu Lim:
Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(7): 1957-1970 (2024) - [j2]Sergio Mazzola, Samuel Riedel, Luca Benini:
Enabling Efficient Hybrid Systolic Computation in Shared-L1-Memory Manycore Clusters. IEEE Trans. Very Large Scale Integr. Syst. 32(9): 1602-1615 (2024) - [c12]Samuel Riedel, Marc Gantenbein, Alessandro Ottaviano, Torsten Hoefler, Luca Benini:
LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems Through Polling-Free and Retry-Free Operation. DATE 2024: 1-6 - [c11]Yichao Zhang, Marco Bertuletti, Samuel Riedel, Matheus A. Cavalcante, Alessandro Vanelli-Coralli, Luca Benini:
TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios. ACM Great Lakes Symposium on VLSI 2024: 86-91 - [c10]Sudipta Das, Samuel Riedel, Marco Bertuletti, Luca Benini, Moritz Brunion, Julien Ryckaert, James Myers, Dwaipayan Biswas, Dragomir Milojevic:
3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs. ISCAS 2024: 1-5 - [i11]Samuel Riedel, Marc Gantenbein, Alessandro Ottaviano, Torsten Hoefler, Luca Benini:
LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation. CoRR abs/2401.09359 (2024) - [i10]Sergio Mazzola, Samuel Riedel, Luca Benini:
Enabling Efficient Hybrid Systolic Computation in Shared L1-Memory Manycore Clusters. CoRR abs/2402.12986 (2024) - [i9]Yichao Zhang, Marco Bertuletti, Samuel Riedel, Matheus A. Cavalcante, Alessandro Vanelli-Coralli, Luca Benini:
TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios. CoRR abs/2405.04988 (2024) - [i8]Yichao Zhang, Marco Bertuletti, Chi Zhang, Samuel Riedel, Alessandro Vanelli-Coralli, Luca Benini:
A 1024 RV-Cores Shared-L1 Cluster with High Bandwidth Memory Link for Low-Latency 6G-SDR. CoRR abs/2408.08882 (2024) - 2023
- [j1]Samuel Riedel, Matheus A. Cavalcante, Renzo Andri, Luca Benini:
MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory. IEEE Trans. Computers 72(12): 3561-3575 (2023) - [c9]Samuel Riedel, Gua Hao Khov, Sergio Mazzola, Matheus A. Cavalcante, Renzo Andri, Luca Benini:
MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster. DATE 2023: 1-2 - [c8]Samuel Riedel, Matheus A. Cavalcante, Manos Frouzakis, Domenic Wüthrich, Enis Mustafa, Arlind Billa, Luca Benini:
MinPool: A 16-core NUMA-L1 Memory RISC-V Processor Cluster for Always-on Image Processing in 65nm CMOS. ICECS 2023: 1-4 - [c7]Marco Bertuletti, Samuel Riedel, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini:
Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster. SAMOS 2023: 241-254 - [i7]Samuel Riedel, Matheus A. Cavalcante, Renzo Andri, Luca Benini:
MemPool: A Scalable Manycore Architecture with a Low-Latency Shared L1 Memory. CoRR abs/2303.17742 (2023) - [i6]Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel, Alessandro Ottaviano, Andreas Kurth, Torsten Hoefler, Luca Benini:
A High-performance, Energy-efficient Modular DMA Engine Architecture. CoRR abs/2305.05240 (2023) - [i5]Marco Bertuletti, Samuel Riedel, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini:
Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster. CoRR abs/2307.10248 (2023) - [i4]Matheus A. Cavalcante, Matteo Perotti, Samuel Riedel, Luca Benini:
Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency. CoRR abs/2309.10137 (2023) - 2022
- [c6]Matheus A. Cavalcante, Anthony Agnesina, Samuel Riedel, Moritz Brunion, Alberto García-Ortiz, Dragomir Milojevic, Francky Catthoor, Sung Kyu Lim, Luca Benini:
MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration. DATE 2022: 394-399 - [c5]Matheus A. Cavalcante, Domenic Wüthrich, Matteo Perotti, Samuel Riedel, Luca Benini:
Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters. ICCAD 2022: 22:1-22:9 - [c4]Anthony Agnesina, Moritz Brunion, Alberto García Ortiz, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Matheus A. Cavalcante, Samuel Riedel, Luca Benini, Sung Kyu Lim:
Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs. ISLPED 2022: 15:1-15:6 - [i3]Matheus A. Cavalcante, Domenic Wüthrich, Matteo Perotti, Samuel Riedel, Luca Benini:
Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters. CoRR abs/2207.07970 (2022) - 2021
- [c3]Matheus A. Cavalcante, Samuel Riedel, Antonio Pullini, Luca Benini:
MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect. DATE 2021: 701-706 - [c2]Samuel Riedel, Fabian Schuiki, Paul Scheffler, Florian Zaruba, Luca Benini:
Banshee: A Fast LLVM-Based RISC-V Binary Translator. ICCAD 2021: 1-9 - [i2]Matheus A. Cavalcante, Anthony Agnesina, Samuel Riedel, Moritz Brunion, Alberto García-Ortiz, Dragomir Milojevic, Francky Catthoor, Sung Kyu Lim, Luca Benini:
MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration. CoRR abs/2112.01168 (2021) - 2020
- [c1]Andreas Kurth, Samuel Riedel, Florian Zaruba, Torsten Hoefler, Luca Benini:
ATUNs: Modular and Scalable Support for Atomic Operations in a Shared Memory Multiprocessor. DAC 2020: 1-6 - [i1]Matheus A. Cavalcante, Samuel Riedel, Antonio Pullini, Luca Benini:
MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect. CoRR abs/2012.02973 (2020)
Coauthor Index
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last updated on 2024-10-01 20:47 CEST by the dblp team
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