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Amir Masoud Gharehbaghi
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2020 – today
- 2020
- [j10]Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita:
A Logic Optimization Method by Eliminating Redundant Multiple Faults from Higher to Lower Cardinality. IPSJ Trans. Syst. LSI Des. Methodol. 13: 35-38 (2020) - [j9]Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita:
An Automatic Test Pattern Generation Method for Multiple Stuck-At Faults by Incrementally Extending the Test Patterns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2990-2999 (2020) - [c32]Masahiro Fujita, Yusuke Kimura, Xingming Le, Yukio Miyasaka, Amir Masoud Gharehbaghi:
Synthesis and Optimization of Multiple Portions of Circuits for ECO based on Set-Covering and QBF Formulations. DATE 2020: 744-749 - [c31]Akihiro Goda, Yukio Miyasaka, Amir Masoud Gharehbaghi, Masahiro Fujita:
Synthesis and Generalization of Parallel Algorithms Considering Communication Constraints. ISQED 2020: 123-128
2010 – 2019
- 2019
- [j8]Yusuke Kimura, Amir Masoud Gharehbaghi, Masahiro Fujita:
Signal Selection Methods for Debugging Gate-Level Sequential Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(12): 1770-1780 (2019) - [j7]Heming Sun, Zhengxue Cheng, Amir Masoud Gharehbaghi, Shinji Kimura, Masahiro Fujita:
Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(4): 1517-1530 (2019) - [c30]Yusuke Kimura, Amir Masoud Gharehbaghi, Masahiro Fujita:
Signal Selection Methods for Efficient Multi-Target Correction. ISCAS 2019: 1-5 - [c29]Tomohiro Maruoka, Yukio Miyasaka, Akihiro Goda, Amir Masoud Gharehbaghi, Masahiro Fujita:
Live Demonstration: Automatic Synthesis of Algorithms on Multi Chip/FPGA with Communication Constraints. ISCAS 2019: 1 - [c28]Qinhao Wang, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita:
High-Level Engineering Change Through Programmable Datapath and SMT Solvers. ISCAS 2019: 1-5 - [c27]Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita:
Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single Faults. ISQED 2019: 284-290 - [c26]Qi Lu, Amir Masoud Gharehbaghi, Masahiro Fujita:
Approximate Arithmetic Circuit Design Using a Fast and Scalable Method. VLSI-SoC 2019: 65-70 - [c25]Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita:
An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults. VTS 2019: 1-6 - 2018
- [j6]Yusuke Kimura, Amir Masoud Gharehbaghi, Masahiro Fujita:
C Description Reconstruction Method from a Revised Netlist for ECO Support. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(4): 685-696 (2018) - [j5]Peikun Wang, Conrad J. Moore, Amir Masoud Gharehbaghi, Masahiro Fujita:
An ATPG Method for Double Stuck-At Faults by Analyzing Propagation Paths of Single Faults. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(3): 1063-1074 (2018) - [c24]Amir Masoud Gharehbaghi, Tomohiro Maruoka, Masahiro Fujita:
A New Reconfigurable Architecture with Applications to IoT and Mobile Computing. IFIPIoT@WCC 2018: 133-146 - 2017
- [c23]Kentaro Iwata, Amir Masoud Gharehbaghi, Mehdi Baradaran Tahoori, Masahiro Fujita:
Post Silicon Debugging of Electrical Bugs Using Trace Buffers. ATS 2017: 189-194 - [c22]Amir Masoud Gharehbaghi, Masahiro Fujita:
A new approach for diagnosing bridging faults in logic designs. ISCAS 2017: 1-4 - [c21]Conrad J. Moore, Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita:
Test pattern generation for multiple stuck-at faults not covered by test patterns for single faults. ISCAS 2017: 1-4 - [c20]Heming Sun, Zhengxue Cheng, Amir Masoud Gharehbaghi, Shinji Kimura, Masahiro Fujita:
A low-cost approximate 32-point transform architecture. ISCAS 2017: 1-4 - [c19]Amir Masoud Gharehbaghi, Masahiro Fujita:
A new approach for selecting inputs of logic functions during debug. ISQED 2017: 166-173 - [c18]Amir Masoud Gharehbaghi, Masahiro Fujita:
A new approach for constructing logic functions after ECO. VLSI-SoC 2017: 1-6 - 2016
- [j4]Amir Masoud Gharehbaghi, Masahiro Fujita:
Fast and Efficient Signature-Based Sub-Circuit Matching. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1355-1365 (2016) - [c17]Amir Masoud Gharehbaghi, Masahiro Fujita:
A New Approach for Debugging Logic Circuits without Explicitly Debugging Their Functionality. ATS 2016: 31-36 - 2015
- [c16]Shridhar Choudhary, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita:
Trace signal selection methods for post silicon debugging. VLSI-SoC 2015: 258-263 - [c15]Amir Masoud Gharehbaghi, Masahiro Fujita:
Efficient signature-based sub-circuit matching. VLSI-SoC 2015: 280-285 - 2014
- [j3]Amir Masoud Gharehbaghi, Masahiro Fujita:
Automatic Rectification of Processor Design Bugs Using a Scalable and General Correction Model. IEICE Trans. Inf. Syst. 97-D(4): 852-863 (2014) - [c14]Amir Masoud Gharehbaghi, Masahiro Fujita:
Specification and formal verification of power gating in processors. ISQED 2014: 604-610 - 2013
- [c13]Satoshi Jo, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita:
Rectification of advanced microprocessors without changing routing on FPGAs (abstract only). FPGA 2013: 279 - [c12]Satoshi Jo, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita:
Debugging processors with advanced features by reprogramming LUTs on FPGA. FPT 2013: 50-57 - 2012
- [j2]Amir Masoud Gharehbaghi, Masahiro Fujita:
Transaction Ordering in Network-on-Chips for Post-Silicon Validation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2309-2318 (2012) - [c11]Amir Masoud Gharehbaghi, Masahiro Fujita:
Error Model Free Automatic Design Error Correction of Complex Processors Using Formal Methods. Asian Test Symposium 2012: 143-148 - [c10]Amir Masoud Gharehbaghi, Masahiro Fujita:
Automatic rectification of design errors in complex processors with programmable hardware. FPT 2012: 141-146 - [c9]Amir Masoud Gharehbaghi, Masahiro Fujita:
Transaction-based post-silicon debug of many-core System-on-Chips. ISQED 2012: 702-708 - 2011
- [c8]Amir Masoud Gharehbaghi, Masahiro Fujita:
Formal verification guided automatic design error diagnosis and correction of complex processors. HLDVT 2011: 121-127 - [c7]Amir Masoud Gharehbaghi, Masahiro Fujita:
Global transaction ordering in Network-on-Chips for post-silicon validation. ISQED 2011: 284-289 - 2010
- [c6]Bijan Alizadeh, Amir Masoud Gharehbaghi, Masahiro Fujita:
Pipelined Microprocessors Optimization and Debugging. ARC 2010: 435-444 - [c5]Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita:
Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only). FPGA 2010: 288
2000 – 2009
- 2009
- [c4]Masahiro Fujita, Yoshihisa Kojima, Amir Masoud Gharehbaghi:
Debugging from high level down to gate level. DAC 2009: 627-630 - [c3]Amir Masoud Gharehbaghi, Masahiro Fujita:
Transaction-based debugging of system-on-chips with patterns. ICCD 2009: 186-192 - 2008
- [c2]Hassan Hatefi-Ardakani, Amir Masoud Gharehbaghi, Shaahin Hessabi:
System-Level Assertion-Based Performance Verification for Embedded Systems. CSICC 2008: 243-250 - [c1]Hassan Hatefi-Ardakani, Amir Masoud Gharehbaghi, Shaahin Hessabi:
Timing verification of distributed network systems at higher levels of abstraction. HLDVT 2008: 101-107 - 2007
- [j1]Amir Masoud Gharehbaghi, Benyamin Hamdin Yaran, Shaahin Hessabi, Maziar Goudarzi:
An assertion-based verification methodology for system-level design. Comput. Electr. Eng. 33(4): 269-284 (2007)
Coauthor Index
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