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ORCIDPablo Robelly
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2000 – 2009
- 2008
[j1]Pablo Robelly, Gordon Cichon, Hendrik Ahlendorf, Gerhard P. Fettweis:
A HW/SW design methodology for embedded SIMD vector signal processors. Int. J. Embed. Syst. 3(3): 160-169 (2008)- [c13]Torsten Limberg, Markus Winter, Marcel Bimberg, Reimund Klemm, Emil Matús, Marcos B. S. Tavares, Gerhard P. Fettweis, Hendrik Ahlendorf, Pablo Robelly:
A fully programmable 40 GOPS SDR single chip baseband for LTE/WiMAX terminals. ESSCIRC 2008: 466-469 - 2006
- [b1]Juan Pablo Robelly:
An algebraic approach for the design and automatic code generation of signal processing algorithms into SIMD vector processors. Dresden University of Technology, 2006, ISBN 978-3-8322-5119-2, pp. 1-156 - [c12]E. Matu, Hendrik Seidel, Torsten Limberg, Pablo Robelly, Gerhard P. Fettweis:
A GFLOPS Vector-DSP for Broadband Wireless Applications. CICC 2006: 543-546 - [c11]Pablo Robelly, Hendrik Seidel, K. C. Chen, Gerhard P. Fettweis:
Energy efficiency vs. programmability trade-off: architectures and design principles. DATE 2006: 587-592 - 2005
- [c10]Arne Lehmann, Juan Pablo Robelly, Gerhard P. Fettweis:
Design and automatic code generation of a two-dimensional fast cosine transform for SIMD DSP architectures. EUSIPCO 2005: 1-4 - [c9]Emil Matús, Gordon Cichon, Hendrik Seidel, Pablo Robelly, Torsten Limberg, Gerhard P. Fettweis:
A Compiler-friendly and Low-power DSP architecture. GI Jahrestagung (1) 2005: 459 - [c8]Juan Pablo Robelly, Gordon Cichon, Hendrik Seidel, Gerhard P. Fettweis:
Design and automatic code generation of the LMS algorithm for SIMD signal processors. ICASSP (5) 2005: 81-84 - [c7]Pablo Robelly, Arne Lehmann, Gerhard P. Fettweis:
Two-Dimensional Fast Cosine Transform for Vector-STA Architectures. SAMOS 2005: 62-71 - 2004
- [c6]Juan Pablo Robelly, Gordon Cichon, Hendrik Seidel, Gerhard P. Fettweis:
Implementation of recursive digital filters into vector SIMD DSP architectures. ICASSP (5) 2004: 165-168 - [c5]Gordon Cichon, Pablo Robelly, Hendrik Seidel, Marcus Bronzel, Gerhard P. Fettweis:
Compiler Scheduling for STA-Processors. PARELEC 2004: 45-50 - [c4]Hendrik Seidel, Gordon Cichon, Pablo Robelly, Marcus Bronzel, Gerhard P. Fettweis:
Hardware / Software Co-Design of a SIMD-DSP-Based DVB-T Receiver. PARELEC 2004: 221-225 - [c3]Pablo Robelly, Gordon Cichon, Hendrik Seidel, Gerhard P. Fettweis:
Automatic Code Generation for SIMD DSP Architectures: An Algebraic Approach. PARELEC 2004: 372-375 - [c2]Gordon Cichon, Pablo Robelly, Hendrik Seidel, Emil Matús, Marcus Bronzel, Gerhard P. Fettweis:
Synchronous Transfer Architecture (STA). SAMOS 2004: 343-352 - [c1]Hendrik Seidel, Emil Matús, Gordon Cichon, Pablo Robelly, Marcus Bronzel, Gerhard P. Fettweis:
Generated DSP Cores for Implementation of an OFDM Communication System. SAMOS 2004: 353-362
Coauthor Index
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