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ORCID29th Asian Test Symposium 2020: Penang, Malaysia
- 29th IEEE Asian Test Symposium, ATS 2020, Penang, Malaysia, November 23-26, 2020. IEEE 2020, ISBN 978-1-7281-7467-9
- Wei Hu
, Lingjuan Wu, Yu Tai, Jing Tan, Jiliang Zhang:
A Unified Formal Model for Proving Security and Reliability Properties. 1-6 - Shao-Chun Hung, Yi-Chen Lu, Sung Kyu Lim, Krishnendu Chakrabarty:
Power Supply Noise-Aware Scan Test Pattern Reshaping for At-Speed Delay Fault Testing of Monolithic 3D ICs *. 1-6 - Michihiro Shintani, Tomoki Mino, Michiko Inoue:
LBIST-PUF: An LBIST Scheme Towards Efficient Challenge-Response Pairs Collection and Machine-Learning Attack Tolerance Improvement. 1-6 - Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka:
Theoretical Analysis on Noise Performance of Modulated Wideband Converters for Analog Testing. 1-6 - Yohei Nakamura, Naotaka Kuroda, Atsushi Yamaguchi, Ken Nakahara, Michihiro Shintani, Takashi Sato:
Influence of Device Parameter Variability on Current Sharing of Parallel-Connected SiC MOSFETs. 1-6 - Arjun Chaudhuri, Chunsheng Liu, Xiaoxin Fan, Krishnendu Chakrabarty:
C-Testing of AI Accelerators *. 1-6 - Gaku Ogihara, Takayuki Nakatani, Akemi Hatta, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Anna Kuwana, Riho Aoki, Shogo Katayama, Jianglin Wei, Yujie Zhao, Jianlong Wang, Kazumi Hatayama, Haruo Kobayashi:
Summing Node Test Method: Simultaneous Multiple AC Characteristics Testing of Multiple Operational Amplifiers. 1-6 - Aoi Ueda, Michihiro Shintani, Michiko Inoue, Takashi Sato:
Measurement of BTI-induced Threshold Voltage Shift for Power MOSFETs under Switching Operation. 1-6 - Yuqian Pan, Haichun Zhang, Mingyang Gong, Zhenglin Liu:
Unexpected Error Explosion in NAND Flash Memory: Observations and Prediction Scheme. 1-6 - Yipei Yang, Jing Ye, Yuan Cao, Jiliang Zhang, Xiaowei Li, Huawei Li, Yu Hu:
Survey: Hardware Trojan Detection for Netlist. 1-6 - Yixuan Zhao, Zhiteng Chao, Jing Ye, Wen Wang, Yuan Cao, Shuai Chen, Xiaowei Li, Huawei Li:
Optimization Space Exploration of Hardware Design for CRYSTALS-KYBER. 1-6 - Aibin Yan, Yan Chen, Jun Zhou, Jie Cui, Tianming Ni, Xiaoqing Wen, Patrick Girard:
A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets. 1-5 - Jiliang Zhang, Shuang Peng, Yupeng Hu, Fei Peng, Wei Hu, Jinmei Lai, Jing Ye, Xiangqi Wang:
HRAE: Hardware-assisted Randomization against Adversarial Example Attacks. 1-6 - Fern Nee Tan, Jia Yun Chuah:
Pre-silicon Noise to Timing Test Methodology. 1-2 - Arbab Alamgir, Abu Khari bin A'Ain, Norlina Paraman, Usman Ullah Sheikh, Ian Andrew Grout:
A comparative analysis of LFSR cascading for hardware efficiency and high fault coverage in BIST applications. 1-5 - Jiang-Tang Xiao, Ting-Shuo Hsu, Christian M. Fuchs, Yu-Teng Chang, Jing-Jia Liou, Harry H. Chen:
An ISA-level Accurate Fault Simulator for System-level Fault Analysis. 1-6 - Koutaro Hachiya:
A Method to Detect Open Defects in Wire Segments of On-Chip Power Grids. 1-6 - Li Qu, Xiaole Cui, Xiaoxin Cui:
A Testability Enhancement Method for the Memristor Ratioed Logic Circuits. 1-6 - Keno Sato, Takayuki Nakatani, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi:
Accurate Testing of Precision Voltage Reference by DC-AC Conversion. 1-2 - Ming Wang, Jian Xiao, Zhikuang Cai:
An effective technique preventing differential cryptanalysis attack. 1-6 - Manas Kumar Parai, Kasturi Ghosh, Hafizur Rahaman:
Potentiality of Data Fusion in Analog Circuit Fault Diagnosis. 1-6 - Masayuki Gondo, Yousuke Miyake, Takaaki Kato, Seiji Kajihara:
On Evaluation for Aging-Tolerant Ring Oscillators with Accelerated Life Test And Its Application to A Digital Sensor. 1-6 - Shi-Yu Huang:
Overview of On-Chip Performance Monitors for Clock Signals. 1-4 - Vinod G. U, Vineesh V. S., Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh:
LUT-based Circuit Approximation with Targeted Error Guarantees. 1-6 - Chih-Yan Liu, Mu-Ting Wu, James Chien-Mo Li, Gaurav Bhargava, Chris Nigh:
Systematic Hold-time Fault Diagnosis and Failure Debug in Production Chips. 1-7 - Takaaki Ibuchi, Tsuyoshi Funaki:
EMI characterization for power conversion circuit with SiC power devices. 1-6 - Shengyu Duan, Peng Wang, Gaole Sai:
BTI Aging Monitoring based on SRAM Start-up Behavior. 1-6 - Jakub Janicki, Grzegorz Mrugalski, Artur Stelmach, Szczepan Urban:
Scan Chain Diagnosis-Driven Test Response Compactor. 1-6 - Yukiko Shibasaki, Koji Asami, Riho Aoki, Akemi Hatta, Anna Kuwana, Haruo Kobayashi:
Analysis and Design of Multi-Tone Signal Generation Algorithms for Reducing Crest Factor. 1-6 - Jin-Fu Li, Tsai-Ling Tsai, Chun-Lung Hsu, Chi-Tien Sun:
Testing of Configurable 8T SRAMs for In-Memory Computing. 1-5 - Ilia Polian, Jens Anders, Steffen Becker, Paolo Bernardi, Krishnendu Chakrabarty, Nourhan Elhamawy, Matthias Sauer, Adit D. Singh, Matteo Sonza Reorda, Stefan Wagner:
Exploring the Mysteries of System-Level Test. 1-6 - Fukashi Morishita, Masanori Otsuka, Wataru Saito:
An ADC Test Technique With Dual-Path/Multi-Functional Fine Pattern Generator Realizing High Accuracy Measurement for CMOS Image Sensor. 1-6 - Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty:
NodeRank: Observation-Point Insertion for Fault Localization in Monolithic 3D ICs∗. 1-6 - Chee Hoo Kok, Soon Ee Ong:
CPU Utilization Micro-Benchmarking for RealTime Workload Modeling. 1-2 - Teo Sje Yin, Soon Ee Ong:
Artificial Neuron Hardware IP Verification. 1-2 - Jun-Yu Yang, Shi-Yu Huang:
Fault and Soft Error Tolerant Delay-Locked Loop. 1-6 - Jian Hu, Yongyang Hu, Long Yu, Haitao Yang, Yun Kang, Jie Cheng:
Validating GCSE in the scheduling of high-level synthesis. 1-6 - Ghazanfar Ali, Leila Bagheriye, Hans A. R. Manhaeve, Hans G. Kerkhoff:
On-chip EOL Prognostics Using Data-Fusion of Embedded Instruments for Dependable MP-SoCs. 1-6 - Gary K.-C. Huang, Dave Y.-W. Lin, John Z.-L. Tang, Charles H.-P. Wen:
SDPTA: Soft-Delay-aware Pattern-based Timing Analysis and Its Path-Fixing Mechanism. 1-6 - Tanusree Kaibartta, G. P. Biswas, Debesh K. Das:
Heuristic Approach for Identification of Random TSV Defects in 3D IC During Pre-bond Testing. 1-6
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