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ORCIDReConFig 2015: Riviera Maya, Mexico
- Michael Hübner, Maya B. Gokhale, René Cumplido:
International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015, Riviera Maya, Mexico, December 7-9, 2015. IEEE 2015, ISBN 978-1-4673-9406-2 - Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano:
A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2. 1-6 - Viorel Suse, Dan Ionescu:
A real-time reconfigurable architecture for face detection. 1-6 - Omar W. Ibraheem, Arif Irwansyah, Jens Hagemeyer, Mario Porrmann
, Ulrich Rückert:
A resource-efficient multi-camera GigE vision IP core for embedded vision processing platforms. 1-6 - Ekawat Homsirikamol, William Diehl, Ahmed Ferozpuri, Farnoud Farahmand, Malik Umar Sharif, Kris Gaj:
A universal hardware API for authenticated ciphers. 1-8 - Osama G. Attia, Alex Grieve, Kevin R. Townsend, Phillip H. Jones, Joseph Zambreno:
Accelerating all-pairs shortest path using a message-passing reconfigurable architecture. 1-6 - Roberto de Lima, José Martínez-Carranza, Alicia Morales-Reyes, René Cumplido:
Accelerating the construction of BRIEF descriptors using an FPGA-based architecture. 1-6 - Siddharth S. Bhargav, Rishvanth K. Prabakar, Young H. Cho:
Accurate in-situ runtime measurement of energy per operation of system-on-chip on FPGA. 1-8 - Hongyuan Ding, Miaoqing Huang:
Achieving energy-efficiency on MPSoCs: performance and power optimizations. 1-7 - Nikhil Thomas, Andrew Felder, Christophe Bobda:
Adaptive controller using runtime partial hardware reconfiguration for unmanned aerial vehicles (UAVs). 1-7 - Stefan Gehrer, Sebastien Leger, Georg Sigl:
Aging effects on ring-oscillator-based physical unclonable functions on FPGAs. 1-6 - L. Canche Santos, Alejandro Castillo Atoche, J. Vazquez Castillo, Omar Longoria-Gandara, Roberto Carrasco-Alvarez, Jaime Ortegón-Aguilar:
An improved hardware design for matrix inverse based on systolic array QR decomposition and piecewise polynomial approximation. 1-6 - Christopher Blochwitz, Jan Moritz Joseph, Rico Backasch, Thilo Pionteck, Stefan Werner, Dennis Heinrich, Sven Groppe:
An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases. 1-7 - Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Luján:
Analysis of FPGA and software approaches to simulate unconventional computer architectures. 1-8 - Sen Ma, Hongyuan Ding, Miaoqing Huang, David Andrews:
Archborn: an open source tool for automated generation of chip heterogeneous multiprocessor architectures. 1-6 - Thaddeus Koehn, Peter Athanas:
Buffering strategies for ultra high-throughput stream processing. 1-7 - Burak Erbagci, Mudit Bhargava, Rachel Dondero, Ken Mai:
Deeply hardware-entangled reconfigurable logic and interconnect. 1-8 - Poona Bahrebar, Dirk Stroobandt:
Design and exploration of routing methods for NoC-based multicore systems. 1-4 - Alfonso Rodríguez, Juan Valverde, Eduardo de la Torre:
Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs. 1-7 - Zoltán Endre Rákossy, Axel Acosta-Aponte, Tobias G. Noll, Gerd Ascheid, Rainer Leupers, Anupam Chattopadhyay:
Design and synthesis of reconfigurable control-flow structures for CGRA. 1-8 - Sam Skalicky, Tejaswini Ananthanarayana, Sonia López, Marcin Lukowiak:
Designing customized ISA processors using high level synthesis. 1-6 - Rico Backasch, Gerald Hempel, Christopher Blochwitz, Stefan Werner, Sven Groppe, Thilo Pionteck:
An architectural template for composing application specific datapaths at runtime. 1-6 - Johanna Sepúlveda, Daniel Flórez, Guy Gogniat:
Efficient and flexible NoC-based group communication for secure MPSoCs. 1-6 - Thaddeus Koehn, Matthew Carrick, Peter Athanas:
An efficient structure for run-time configuration of synthesis and channelizer filter banks. 1-6 - Vincent Mirian, Paul Chow:
Evaluating shared virtual memory in an OpenCL framework for embedded systems on FPGAs. 1-8 - Riccardo Cattaneo, Gabriele Pallotta, Donatella Sciuto, Marco D. Santambrogio:
Explicitly isolating data and computation in high level synthesis: the role of polyhedral framework. 1-6 - Hongyuan Ding, Miaoqing Huang:
Exploiting hardware abstraction for hybrid parallel computing framework. 1-7 - Javier Alejandro Varela, Christian Brugger, Christian de Schryver, Norbert Wehn, Songyin Tang, Steffen Omland:
Exploiting the brownian bridge technique to improve longstaff-schwartz american option pricing on FPGA systems. 1-6 - Vincent Migliore, Maria Mendez Real, Vianney Lapotre, Arnaud Tisserand, Caroline Fontaine, Guy Gogniat:
Exploration of polynomial multiplication algorithms for homomorphic encryption schemes. 1-6 - Subhadeep Banik, Andrey Bogdanov, Francesco Regazzoni:
Exploring the energy consumption of lightweight blockciphers in FPGA. 1-6 - Marc Reichenbach, Tobias Lieske, Steffen Vaas, Konrad Häublein, Dietmar Fey:
FAUPU - A design framework for the development of programmable image processing architectures. 1-8 - Lukas Johannes Jung, Christian Hochberger:
Feasibility of high level compiler optimizations in online synthesis. 1-7 - Joshua Mack, Sam Bellestri, Daniel Llamocca:
Floating point CORDIC-based architecture for powering computation. 1-6 - Alexander Boschmann, Andreas Agne, Linus Witschen, Georg Thombansen, Florian Kraus, Marco Platzner:
FPGA-based acceleration of high density myoelectric signal processing. 1-8 - Arif Irwansyah, Omar W. Ibraheem, Jens Hagemeyer, Mario Porrmann, Ulrich Rückert:
FPGA-based circular hough transform with graph clustering for vision-based multi-robot tracking. 1-8 - Javier Pérez, Aiman Alabdo, Gabriel J. García, Jorge Pomares, Fernando Torres Medina:
FPGA-based visual control of robot manipulators using dynamic perceptibility. 1-7 - Luis Contreras, Sérgio Cruz, José Maurício S. T. Motta, Carlos H. Llanos:
FPGA implementation of the EKF algorithm for localization in mobile robotics using a unified hardware module approach. 1-6 - Armando Astarloa, Naiara Moreira, Unai Bidarte, Marcelo Urbina, David Modrono:
FPGA based nodes for sub-microsecond synchronization of cyber-physical production systems on high availability ring networks. 1-6 - Andrew Bean, Nachiket Kapre, Peter Y. K. Cheung:
G-DMA: improving memory access performance for hardware accelerated sparse graph computation. 1-6 - Carl Ahlberg, Fredrik Ekstrand, Mikael Ekström, Giacomo Spampinato, Lars Asplund:
GIMME2 - an embedded system for stereo vision and processing of megapixel images with FPGA-acceleration. 1-8 - Festus Hategekimana, Adil Tbatou, Christophe Bobda, Charles A. Kamhoua, Kevin A. Kwiat:
Hardware isolation technique for IRC-based botnets detection. 1-6 - Da Tong, Viktor K. Prasanna:
High throughput sketch based online heavy change detection on FPGA. 1-8 - Benjamin Buhrow, Karl E. Fritz, Barry K. Gilbert, Erik S. Daniel:
A highly parallel AES-GCM core for authenticated encryption of 400 Gb/s network protocols. 1-7 - Ajitesh Srivastava, Ren Chen, Viktor K. Prasanna, Charalampos Chelmis:
A hybrid design for high performance large-scale sorting on FPGA. 1-6 - Pongstorn Maidee, Alireza Kaviani:
Improving FPGA NoC performance using virtual cut-through switching technique. 1-6 - Sang Woo Jun, Chanwoo Chung, Arvind:
Large-scale high-dimensional nearest neighbor search using flash memory with in-store processing. 1-8 - Mario Ruiz, Gustavo Sutter, Sergio López-Buedo, Javier Ramos, Jorge E. López de Vergara, Javier Aracil:
Leveraging open source platforms and high-level synthesis for the design of FPGA-based 10 GbE active network probes. 1-6 - Jean-Pierre David:
Low latency solver for linear equation systems in floating point arithmetic. 1-7 - Amit Kulkarni, Kizheppatt Vipin, Dirk Stroobandt:
MiCAP: a custom reconfiguration controller for dynamic circuit specialization. 1-6 - Enrico A. Deiana, Marco Rabozzi, Riccardo Cattaneo, Marco D. Santambrogio:
A multiobjective reconfiguration-aware scheduler for FPGA-based heterogeneous architectures. 1-6 - Joost Hoozemans, Jens Johansen, Jeroen van Straten, Anthony Brandon, Stephan Wong:
Multiple contexts in a multi-ported VLIW register file implementation. 1-6 - Giulia Gnemmi, Mattia Crippa, Gianluca Durelli, Riccardo Cattaneo, Gabriele Pallotta, Marco D. Santambrogio:
On how to efficiently accelerate brain network analysis on FPGA-based computing system. 1-6 - Juri Schmidt, Ulrich Brüning:
openHMC - a configurable open-source hybrid memory cube controller. 1-6 - Shijie Zhou, Charalampos Chelmis, Viktor K. Prasanna:
Optimizing memory performance for FPGA implementation of pagerank. 1-6 - Sven Hager, Daniel Bendyk, Björn Scheuermann:
Partial reconfiguration and specialized circuitry for flexible FPGA-based packet processing. 1-6 - Jose Fernando Zazo, Sergio López-Buedo, Yury Audzevich, Andrew W. Moore:
A PCIe DMA engine to support the virtualization of 40 Gbps FPGA-accelerated network appliances. 1-6 - C. Jayet-Griffon, Marie-Angela Cornelie, Paolo Maistri, Philippe Elbaz-Vincent, Régis Leveugle:
Polynomial multipliers for fully homomorphic encryption on FPGA. 1-6 - Amit Kulkarni, Robin Bonamy, Dirk Stroobandt:
Power measurements and analysis for dynamic circuit specialization. 1-6 - Tiziana Fanni, Carlo Sau, Paolo Meloni, Luigi Raffo, Francesca Palumbo:
Power modelling for saving strategies in coarse grained reconfigurable systems. 1-4 - Henitsoa Rakotomalala, Xuan Thuy Ngo, Zakaria Najm, Jean-Luc Danger, Sylvain Guilley:
Private circuits II versus fault injection attacks. 1-9 - Jens Rettkowski, Andrew Boutros, Diana Göhringer:
Real-time pedestrian detection on a xilinx zynq using the HOG algorithm. 1-8 - Oskar Mencer:
Keynote 1 - From data to information to flow. 1 - Gordon Ghiu:
Keynote 2 - Towards datacenter computing with FPGAs. 1 - Maya B. Gokhale, Michael Hübner, René Cumplido:
Message from chairs. 1 - Carlo Sau, Luca Fanni, Paolo Meloni, Luigi Raffo, Francesca Palumbo:
Reconfigurable coprocessors synthesis in the MPEG-RVC domain. 1-8 - Hugo A. Andrade, Patricia Derler, John C. Eidson, Ya-Shian Li-Baboud, Aviral Shrivastava, Kevin B. Stanton, Marc Weiss:
Towards a reconfigurable distributed testbed to enable advanced research and development of timing and synchronization in cyber-physical systems. 1-6 - Zhongyuan Zhao, Weiguang Sheng, Naifeng Jing, Weifeng He, Zhigang Mao:
Resource-saving compile flow for coarse-grained reconfigurable architectures. 1-8 - Hamza Bendaoudi, Qifeng Gan, Farida Cheriet, Houssem Ben Tahar, J. M. Pierre Langlois:
A run-length encoding co-processor for retinal image texture analysis. 1-6 - Bruno A. Silva, Alexandre C. B. Delbem, Vanderlei Bonato, Pedro C. Diniz:
Runtime mapping and scheduling for energy efficiency in heterogeneous multi-core systems. 1-6 - Ryan Pattison, Christian Fobel, Gary William Grewal, Shawki Areibi:
Scalable analytic placement for FPGA on GPGPU. 1-6 - Timo Jaeschke, Patrick Imberg, Michael Zapke, Michael Hübner, Nils Pohl:
Scalable modular hardware platform for FPGA based industrial radar flowmeters. 1-6 - Kevin Lee, Peter Athanas:
Shape exploration for modules in rapid assembly workflows. 1-7 - Michal Varchola, Milos Drutarovský, Marek Repka, Pavol Zajac:
Side channel attack on multiprecision multiplier used in protected ECDSA implementation. 1-6 - Pei Zhang, Aaron Mills, Joseph Zambreno, Phillip H. Jones:
A software configurable and parallelized coprocessor architecture for LQR control. 1-8 - Anthony Brandon, Joost Hoozemans, Jeroen van Straten, Arthur Francisco Lorenzon, Anderson Luiz Sartor, Antonio Carlos Schneider Beck, Stephan Wong:
A sparse VLIW instruction encoding scheme compatible with generic binaries. 1-7 - Andrew Powell, Dennis Silage:
Statistical performance of the ARM cortex A9 accelerator coherency port in the xilinx zynq SoC for real-time applications. 1-6 - Maxime Lecomte, Jacques J. A. Fournier, Philippe Maurine:
Thoroughly analyzing the use of ring oscillators for on-chip hardware trojan detection. 1-6 - Joshua S. Monson, Brad L. Hutchings:
Using shadow pointers to trace C pointer values in FPGA circuits. 1-6 - Syed Waqar Nabi, Wim Vanderbauwhede:
Using type transformations to generate program variants for FPGA design space exploration. 1-6 - Vincent Mirian, Paul Chow:
UT-OCL: an OpenCL framework for embedded systems using xilinx FPGAs. 1-6
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