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ORCID35th SBCCI 2022: Porto Alegre, Brazil
- 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, SBCCI 2022, Porto Alegre, Brazil, August 22-26, 2022. IEEE 2022, ISBN 978-1-6654-8128-1
- Thomas Soupizet
, Zalfa Jouni, Joao Frischenbruder Sulzbach, Aziz Benlarbi-Delaï, Pietro M. Ferreira:
Deep Neural Network Feasibility Using Analog Spiking Neurons. 1-6 - Vu Trung Duong Le, Pham Hoai Luan, Thi Hong Tran, Yasuhiko Nakashima:
CSIP: A Compact Scrypt IP design with single PBKDF2 core for Blockchain mining. 1-6 - Carlos Gabriel de Araujo Gewehr, Carlis Raupp, Julio Leão:
eSi-BTC: an energy efficient Bitcoin mining core. 1-6 - Roberta Palau, Wagner Penny, Jones Goebel, Eduardo Zummach, Guilherme Corrêa, Marcelo Schiavon Porto, Luciano Agostini:
Hardware Design for the Separable Symmetric Normalized Wiener Filter of the AV1 Decoder. 1-6 - Bruno Canal, Hamilton Duarte Klimach, Sergio Bampi, Tiago R. Balen:
Time Assisted SAR ADC with Bit-guess and Digital Error Correction. 1-6 - Hugo Rodríguez, Jimmy Tarrillo:
Energy-Efficient Forwarding Routing Algorithm with bidirectional link quality estimator for Wireless Sensor Networks. 1-6 - Anderson R. P. Domingues, Sergio Johann Filho, Alexandre de Morais Amory, Fernando Gehm Moraes:
Design-Time Analysis of Real-Time Traffic for Networks-on-Chip using Constraint Models. 1-6 - Tiago Knorst, Guilherme Korol, Michael Guilherme Jordan, Julio Costella Vicenzi, Arthur Francisco Lorenzon, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
On the benefits of Collaborative Thread Throttling and HLS-Versioning in CPU-FPGA Environments. 1-6 - Marampally Saikiran, Mona Ganji, Degang Chen:
A Time-Efficient Defect Simulation Framework for Analog and Mixed Signal (AMS) Circuits. 1-6 - Peng-Yu Chen, Chih Hsuan Lin, Wen-Hsiao Peng:
A Study of Motion Coding Schemes for Learned Video Compression. 1-6 - Orazio Aiello, Paolo Crovetti, Massimo Alioto:
Conversion Time-Power Tradeoff in Capacitance-to-Digital Converters with Dual-Mode Logic. 1-5 - Jones Goebel, Luciano Agostini, Bruno Zatt, Marcelo Schiavon Porto:
Low-Frequency Non-Separable Transform Hardware System Design for the VVC Encoder. 1-6 - Hector Gerardo Muñoz Hernandez, Florian Fricke, Muhammed Al Kadi, Marc Reichenbach, Michael Hübner:
Edge GPU based on an FPGA Overlay Architecture using PYNQ. 1-6 - Jader A. De Lima:
A 0.55-V Oscillator with Improved Stability Against Temperature and Supply-Voltage Variations. 1-6 - Frederik Kautz, Holger Blume, Christian Sauer:
Methodology for an Early Exploration of Embedded Systems using Portable Test and Stimulus Standard. 1-6 - Luis Felipe Machado Dutra, Alessandro Gonçalves Girardi, Lucas Compassi Severo:
A 0.3 to 5-MHz Low-Voltage Digitally-Controlled Oscillator for Energy Harvesting Applications. 1-6 - Suoyue Zhan, Chunhong Chen:
Circuit Reliability Analysis with Considerations of Aging Effect. 1-5 - Gabriel Henrique Eisenkraemer, Leonardo Londero de Oliveira, Everton Alceu Carara:
Comparative Analysis of Hardware Implementations of a Convolutional Neural Network. 1-6 - Iacana Ianiski Weber, Angelo Elias Dalzotto, Fernando Gehm Moraes:
A High-level Model to Leverage NoC-based Many-core Research. 1-6 - Roberta Palau, Jones Goebel, Eduardo Zummach, Ramiro Viana, Marcel Moscarelli Corrêa, Guilherme Corrêa, Marcelo Schiavon Porto, Luciano Agostini:
An UHD 4K@60fps Dual Self-Guided Filter Targeting the AV1 Decoder. 1-6 - Susann Rothe, Jens Lienig:
Reliability by Design: Avoiding Migration-Induced Failure in IC Interconnects. 1-6 - Carlos Salazar-García, Alfonso Chacón-Rodríguez, Renato Rimolo-Donadio, Ronny García-Ramírez, David Solórzano-Pacheco, Jeferson González-Gómez, Christos Strydis:
A custom interconnection multi-FPGA framework for distributed processing applications. 1-6 - Matheus Cortez, Alessandro Gonçalves Girardi, Paulo César Comassetto de Aguirre:
High-Level Design of a 14-bit Continuous-Time Sigma-Delta Modulator with FIR DAC for Low-Voltage Audio Devices. 1-6 - Rafael N. M. Oliveira, Fábio G. R. G. da Silva, Ricardo Reis, Rafael B. Schvittz, Cristina Meinhardt:
Improving Soft Error Robustness of Full Adder Circuits with Decoupling Cell and Transistor Sizing. 1-6 - Leonardo Rodrigues Leopoldo, Wilhelmus A. M. Van Noije:
Low Noise Broadband Amplifier for Breast Cancer System. 1-5 - Hammam Kattan, Hussam Amrouch:
Advanced Thermal Management using Approximate Computing and On-Chip Thermoelectric Cooling. 1-6 - Marampally Saikiran, Mona Ganji, Degang Chen:
Digital Defect-Oriented Test Methodology for Flipped Voltage Follower Low Dropout (LDO) Voltage Regulators. 1-6 - Rafael Follmann Faccenda, Gustavo Comarú, Luciano Lores Caimi, Fernando Gehm Moraes:
Secure Communication with Peripherals in NoC-based Many-cores. 1-6 - Sandro M. Marques, Fábio D. Rossi, Marcelo Caggiani Luizelli, Antonio Carlos Schneider Beck, Arthur Francisco Lorenzon:
Thermal-Aware Thread and Turbo Frequency Throttling Optimization for Parallel Applications. 1-6 - Reza Ranjandish:
An All-digital Programmable Current-limited Discharge Circuitry for a Safe Electrical Stimulation. 1-4 - Zalfa Jouni, Thomas Soupizet, Siqi Wang, Aziz Benlarbi-Delaï, Pietro M. Ferreira:
1.2 nW Neuromorphic Enhanced Wake-Up Radio. 1-6 - Shengyu Duan, Gaole Sai:
Protecting SRAM PUF from BTI Aging-based Cloning Attack. 1-6 - Andrea Ballo, Alfio Dario Grasso, Marco Privitera:
A Design Procedure for Sizing Comparators in Active Rectifiers using $g_{m}/I_{D}$ Technique. 1-6 - Rodrigo N. Wuerdig, Bruno Canal, Tiago R. Balen, Sergio Bampi:
Designing a 9.3μW Low-Power Time-to-Digital Converter (TDC) for a Time Assisted SAR ADC. 1-6 - Timothy Martin, Charlotte Barnes, Gary William Grewal, Shawki Areibi:
Integrating Machine-Learning Probes into the VTR FPGA Design Flow. 1-6 - Gayas Mohiuddin Sayed, Matthias Kuhl:
Miniaturized Sign-Magnitude Stochastic-Binary FIR Filter Architecture with Enhanced Accuracy. 1-6 - Marcel Moscarelli Corrêa, Daniel Palomino, Guilherme Corrêa, Luciano Agostini:
Direction-Based Fast Mode Decision and Hardware Design for the AV1 Intra Prediction. 1-6 - Mariana Siniscalchi, Carlos Galup-Montoro, Sylvain Bourdel, Fernando Silveira:
Limits for Low Supply Voltage Operation of a 5 GHz VCO to Drive a 4-Path Mixer. 1-5 - Daiane Freitas, Bruna Nagai, Mateus Grellert, Cláudio Machado Diniz, Guilherme Corrêa:
High-Throughput Multifilter VLSI Design for the AV1 Fractional Motion Estimation. 1-6 - Marcello M. Muñoz, Henrique Kessler, Marcelo Schiavon Porto, Vinicius V. Camargo:
Transistor Reordering for Electrical Improvement in CMOS Complex Gates. 1-6 - Pham Hoai Luan, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima:
A Flexible and Energy-Efficient BLAKE-256/2s Co-Processor for Blockchain-based IoT Applications. 1-6 - Marcos Luiggi Lemos Sartori, Willian Analdo Nunes, Ney Laert Vilar Calazans:
Enhancing an Asynchronous Circuit Design Flow to Support Complex Digital System Design. 1-6 - Alcides S. Costa, Leonardo Droves Silveira, André Inácio Reis:
A Virtual Board Approach for Prototyping and Teaching Digital Design. 1-6 - Julian Haase, Alexander Groß, Maximilian Feichter, Diana Göhringer:
PANACA: An Open-Source Configurable Network-on-Chip Simulation Platform. 1-6 - Gabriel Lima Jacinto, Lucas Yuki Imamura, Mateus Grellert, Cristina Meinhardt:
Exploring Machine Learning for Electrical Behavior Prediction: The CMOS Inverter Case Study. 1-6 - Konstantinos Antonopoulos, Dimitris Karadimas, Alexandros Spournias, Christos Panagiotou, Ignantios Fwtiou, Ioannis Symeonidis, Christos P. Antonopoulos, Michael Hübner, Nikolaos S. Voros:
A distributed Embedded Systems IoT platform and Associated services Supporting Shopping Cart for Disabled People. 1-6 - Matheus Isquierdo, Renira Soares, Felipe Sampaio, Bruno Zatt, Daniel Palomino:
Error Resilience Evaluation of Approximate Storage in the Intra Prediction of VVC Decoders. 1-6
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last updated on 2024-10-18 19:34 CEST by the dblp team
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