Article

Fighting the memory wall with assisted execution

Author:

Michel DuboisAuthors Info & Claims

CF '04: Proceedings of the 1st conference on Computing frontiers

Pages 168 - 180

https://doi.org/10.1145/977091.977116

Published: 14 April 2004 Publication History

Abstract

Assisted execution is a form of simultaneous multithreading in which a set of auxiliary "assistant" threads, called nanothreads, is attached to each thread of an application. Nanothreads are lightweight threads which run on the same processor as the main (application) thread and help execute the main thread as fast as possible. Nanothreads exploit resources that are idled in the processor because of hazards due to program dependencies and memory access delays.Assisted execution has the potential to alter the current trade-offs between static and dynamic execution mechanisms. Nanothreads can monitor and reconfigure the underlying hardware, can emulate hardware and can profile applications with little or no interference to improve the program on-line or off-line.We demonstrate the power of assisted execution with an important application, namely data prefetching to fight the memory wall problem. Simulation results on several SPEC95 benchmarks show that sequential and stride prefetching implemented with nanothreads performs just as well as ideal hardware prefetchers.

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Cited By

Darabi SSadrosadati MAkbarzadeh NLindegger JHosseini MPark JGomez-Luna JMutlu OSarbazi-Azad H(2022)Morpheus: Extending the Last Level Cache Capacity in GPU Systems Using Idle GPU Core Resources2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO56248.2022.00029(228-244)Online publication date: Oct-2022
https://doi.org/10.1109/MICRO56248.2022.00029
Vijaykumar NPekhimenko GJog ABhowmick AAusavarungnirun RDas CKandemir MMowry TMutlu O(2015)A case for core-assisted bottleneck acceleration in GPUsACM SIGARCH Computer Architecture News10.1145/2872887.275039943:3S(41-53)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2872887.2750399
Vijaykumar NPekhimenko GJog ABhowmick AAusavarungnirun RDas CKandemir MMowry TMutlu OMarr DAlbonesi D(2015)A case for core-assisted bottleneck acceleration in GPUsProceedings of the 42nd Annual International Symposium on Computer Architecture10.1145/2749469.2750399(41-53)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2749469.2750399
Show More Cited By

Index Terms

Fighting the memory wall with assisted execution
1. Computer systems organization
  1. Architectures
    1. Serial architectures
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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Published In

cover image ACM Conferences

CF '04: Proceedings of the 1st conference on Computing frontiers

April 2004

522 pages

ISBN:1581137419

DOI:10.1145/977091

General Chair:
Stamatis Vassiliadis
Delft University of Technology, The Netherlands
,
Program Chairs:
Jean-Luc Gaudiot
University of California at Irvine, USA
,
Vincenzo Piuri
University of Milan, Italy

Copyright � 2004 ACM.

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Publication History

Published: 14 April 2004

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CF04: Computing Frontiers Conference

April 14 - 16, 2004

Ischia, Italy

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Overall Acceptance Rate 273 of 785 submissions, 35%

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Cited By

Darabi SSadrosadati MAkbarzadeh NLindegger JHosseini MPark JGomez-Luna JMutlu OSarbazi-Azad H(2022)Morpheus: Extending the Last Level Cache Capacity in GPU Systems Using Idle GPU Core Resources2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO56248.2022.00029(228-244)Online publication date: Oct-2022
https://doi.org/10.1109/MICRO56248.2022.00029
Vijaykumar NPekhimenko GJog ABhowmick AAusavarungnirun RDas CKandemir MMowry TMutlu O(2015)A case for core-assisted bottleneck acceleration in GPUsACM SIGARCH Computer Architecture News10.1145/2872887.275039943:3S(41-53)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2872887.2750399
Vijaykumar NPekhimenko GJog ABhowmick AAusavarungnirun RDas CKandemir MMowry TMutlu OMarr DAlbonesi D(2015)A case for core-assisted bottleneck acceleration in GPUsProceedings of the 42nd Annual International Symposium on Computer Architecture10.1145/2749469.2750399(41-53)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2749469.2750399
Dud�s �Juh�sz S(2012)Reconfigurable Preexecution in Data Parallel Applications on Multicore SystemsElectrical Engineering and Intelligent Systems10.1007/978-1-4614-2317-1_3(29-38)Online publication date: 2-May-2012
https://doi.org/10.1007/978-1-4614-2317-1_3
Dud�s �Juh�sz SSchr�di T(2011)Software Controlled Adaptive Pre-Execution for Data PrefetchingInternational Journal of Parallel Programming10.1007/s10766-011-0190-540:4(381-396)Online publication date: 30-Oct-2011
https://doi.org/10.1007/s10766-011-0190-5
Qiu XDubois M(2005)Moving Address Translation Closer to Memory in Distributed Shared-Memory MultiprocessorsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2005.8416:7(612-623)Online publication date: 1-Jul-2005
https://dl.acm.org/doi/10.1109/TPDS.2005.84
Lu JDas AHsu WNguyen KAbraham S(2005)Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP ProcessorProceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2005.18(93-104)Online publication date: 12-Nov-2005
https://dl.acm.org/doi/10.1109/MICRO.2005.18
Barnes RRyoo SHwu W(2005)"Flea-flicker" Multipass PipeliningProceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2005.1(319-330)Online publication date: 12-Nov-2005
https://dl.acm.org/doi/10.1109/MICRO.2005.1

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