Newsletter Downloads
On the Design and Evaluation of a Real-Time Operating System for Cache-Coherent Multicore Architectures
The uncontrolled use of the cache hierarchy in a multicore processor by real-time tasks may impact their worst-case execution times. Several operating system techniques have been recently proposed to deal with caches in a multiprocessor in order to ...
Revisiting Hash Table Design for Phase Change Memory
Phase Change Memory (PCM) is emerging as an attractive alternative to Dynamic Random Access Memory (DRAM) in building data-intensive computing systems. PCM offers read/write performance asymmetry that makes it necessary to revisit the design of in-...
A Fast and Slippery Slope for File Systems
There is a vast number and variety of file systems currently available, each optimizing for an ever growing number of storage devices and workloads. Users have an unprecedented, and somewhat overwhelming, number of data management options. At the same ...
Hardening an L4 Microkernel Against Soft Errors by Aspect-Oriented Programming and Whole-Program Analysis
Transient hardware faults in computer systems have become widespread as shrinking structures and low supply voltages reduce the amount of energy needed to trigger a fault. This paper describes the latest improvements of a software-based fault-tolerance ...
Lightweight Capability Domains: Towards Decomposing the Linux Kernel
Despite a number of radical changes in how computer systems are used, the design principles behind the very core of the systems stack--an operating system kernel--has remained unchanged for decades.We run monolithic kernels developed with a combination ...
Tapir: A Language for Verified OS Kernel Probes
Kernel probes allow code to be inserted into a running operating system kernel to gather information for debugging or profiling. Inserting code into the kernel raises a number of safety issues. Current solutions follow one of the two paths: a VM-based ...
Making Lock-free Data Structures Verifiable with Artificial Transactions
Among all classes of parallel programming abstractions, lock-free data structures are considered one of the most scalable and efficient thanks to their fine-grained style of synchronization. However, they are also challenging for developers and tools to ...
Harnessing Energy Efficiency of Heterogeneous-ISA Platforms
With the emergence of both power and performance as primary design constraints, energy efficiency has become the new design criteria. A platform with heterogeneous-ISA processors can provide multiple power-performance execution points needed for a ...
Sudden Drop in the Battery Level?: Understanding Smartphone State of Charge Anomaly
Battery State of Charge (SOC) estimation is a fundamental component of today's smartphones that affects the internal processes and observable behavior of the devices. This article systematically investigates and analyzes the SOC estimation techniques in ...
Modeling Communication Costs in Blade Servers
Datacenters demand big memory servers for big data. For blade servers, which disaggregate memory across multiple blades, we derive technology and architectural models to estimate communication delay and energy. These models permit new case studies in ...