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MAPS: Optimizing Massively Parallel Applications Using Device-Level Memory Abstraction

Authors:

Tal Ben-NunAuthors Info & Claims

ACM Transactions on Architecture and Code Optimization (TACO), Volume 11, Issue 4

Article No.: 44, Pages 1 - 22

https://doi.org/10.1145/2680544

Published: 08 December 2014 Publication History

Abstract

GPUs play an increasingly important role in high-performance computing. While developing naive code is straightforward, optimizing massively parallel applications requires deep understanding of the underlying architecture. The developer must struggle with complex index calculations and manual memory transfers. This article classifies memory access patterns used in most parallel algorithms, based on Berkeley’s Parallel “Dwarfs.” It then proposes the MAPS framework, a device-level memory abstraction that facilitates memory access on GPUs, alleviating complex indexing using on-device containers and iterators. This article presents an implementation of MAPS and shows that its performance is comparable to carefully optimized implementations of real-world applications.

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Cited By

Calotoiu ABen-Nun TKwasniewski Gde Fine Licht JSchneider TSchaad PHoefler TRauchwerger LCameron KNikolopoulos DPnevmatikatos D(2022)Lifting C semantics for dataflow optimizationProceedings of the 36th ACM International Conference on Supercomputing10.1145/3524059.3532389(1-13)Online publication date: 28-Jun-2022
https://dl.acm.org/doi/10.1145/3524059.3532389
George AManoj SSarkar SNaik RSarkar SHildebrandt TKumar ASharma R(2019)ThrustHeteroProceedings of the 12th Innovations in Software Engineering Conference (formerly known as India Software Engineering Conference)10.1145/3299771.3299773(1-11)Online publication date: 14-Feb-2019
https://dl.acm.org/doi/10.1145/3299771.3299773
Sarkar SAlavani G(2018)How Easy it is to Write Software for Heterogeneous Systems?ACM SIGSOFT Software Engineering Notes10.1145/3149485.314951142:4(1-7)Online publication date: 11-Jan-2018
https://dl.acm.org/doi/10.1145/3149485.3149511
Show More Cited By

Index Terms

MAPS: Optimizing Massively Parallel Applications Using Device-Level Memory Abstraction
1. Computer systems organization
  1. Architectures
    1. Parallel architectures

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Published In

cover image ACM Transactions on Architecture and Code Optimization

ACM Transactions on Architecture and Code Optimization Volume 11, Issue 4

January 2015

797 pages

ISSN:1544-3566

EISSN:1544-3973

DOI:10.1145/2695583

Editor:
Koen De Bosschere
Ghent University

Issue’s Table of Contents

Copyright © 2014 ACM.

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Association for Computing Machinery

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Publication History

Published: 08 December 2014

Accepted: 01 October 2014

Revised: 01 August 2014

Received: 01 May 2014

Published in TACO Volume 11, Issue 4

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Cited By

Calotoiu ABen-Nun TKwasniewski Gde Fine Licht JSchneider TSchaad PHoefler TRauchwerger LCameron KNikolopoulos DPnevmatikatos D(2022)Lifting C semantics for dataflow optimizationProceedings of the 36th ACM International Conference on Supercomputing10.1145/3524059.3532389(1-13)Online publication date: 28-Jun-2022
https://dl.acm.org/doi/10.1145/3524059.3532389
George AManoj SSarkar SNaik RSarkar SHildebrandt TKumar ASharma R(2019)ThrustHeteroProceedings of the 12th Innovations in Software Engineering Conference (formerly known as India Software Engineering Conference)10.1145/3299771.3299773(1-11)Online publication date: 14-Feb-2019
https://dl.acm.org/doi/10.1145/3299771.3299773
Sarkar SAlavani G(2018)How Easy it is to Write Software for Heterogeneous Systems?ACM SIGSOFT Software Engineering Notes10.1145/3149485.314951142:4(1-7)Online publication date: 11-Jan-2018
https://dl.acm.org/doi/10.1145/3149485.3149511
Trois CBona LS. Oliveira LMartinello MHarewood-Gill DD. Del Fabro MNejabati RSimeonidou DD. Lima JStein B(2018)Exploring Textures in Traffic Matrices to Classify Data Center Communications2018 IEEE 32nd International Conference on Advanced Information Networking and Applications (AINA)10.1109/AINA.2018.00161(1123-1130)Online publication date: May-2018
https://doi.org/10.1109/AINA.2018.00161
Sarkar SGeorge AManoj S(2018)Thrust2D: A new design abstraction framework for structured grid class of algorithmsConcurrency and Computation: Practice and Experience10.1002/cpe.474030:19Online publication date: 17-Jul-2018
https://doi.org/10.1002/cpe.4740
Hall MRobins COwens KNowatzke JLauck TSmith L(2017)High performance supercomputing on a budgetJournal of Computing Sciences in Colleges10.5555/3055338.305535432:4(86-92)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.5555/3055338.3055354
George AManoj SGupte SSarkar SKumar ASarkar SGerndt M(2017)How Effective is Design Abstraction in Thrust?Proceedings of the 2017 Workshop on Software Engineering Methods for Parallel and High Performance Applications10.1145/3085158.3086159(3-10)Online publication date: 26-Jun-2017
https://dl.acm.org/doi/10.1145/3085158.3086159
Trois CBona LFabro MMartinello MBidkar SNejabati RSimeonidou D(2017)Softening Up the Network for Scientific Applications2017 25th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP)10.1109/PDP.2017.19(108-115)Online publication date: 2017
https://doi.org/10.1109/PDP.2017.19
George AManoj SGupte SSarkar S(2017)An Empirical Evaluation of Design Abstraction and Performance of Thrust Framework2017 46th International Conference on Parallel Processing Workshops (ICPPW)10.1109/ICPPW.2017.43(233-242)Online publication date: Aug-2017
https://doi.org/10.1109/ICPPW.2017.43
George AManoj SGupte SMitra SSarkar S(2017)Thrust++: Extending Thrust Framework for Better Abstraction and Performance2017 IEEE 24th International Conference on High Performance Computing (HiPC)10.1109/HiPC.2017.00049(368-377)Online publication date: Dec-2017
https://doi.org/10.1109/HiPC.2017.00049
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