skip to main content
research-article

All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits

Published: 13 October 2022 Publication History

Abstract

Recently, spin-transfer torque magnetic cell (STT-mCell) has emerged as a promising spintronic device to be used in Computing-in-Memory (CIM) systems. However, it is challenging to guarantee the hardware security of STT-mCell-based all-spin circuits. In this work, we propose a novel Physical Unclonable Function (PUF) design for the STT-mCell-based all-spin circuit (All-Spin PUF) exploiting the unique manufacturing process variation (PV) on STT-mCell write latency. A methodology is used to select appropriate logic gates in the all-spin chip to generate a unique identification key. A linear feedback shift register (LFSR) initiates the All-Spin PUF and simultaneously generates a 64-bit signature at each clock cycle. Signature generation is stabilized using an automatic write-back technique. In addition, a masking scheme is applied for signature improvement. The uniqueness of the improved signature is 49.61%. With � 20% supply voltage and 5�C to 105�C temperature variations, the All-Spin PUF shows a strong resiliency. In comparison with state-of-the-art PUFs, our approach can reduce hardware overhead effectively. Finally, the robustness of the All-Spin PUF against emerging modeling attacks is verified as well.

References

[1]
B. Yan, F. Chen, Y. Zhang, C. Song, H. Li and Y. Chen. 2018. Exploring the opportunity of implementing neuromorphic computing systems with spintronic devices. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE’18), 109–112.
[2]
F. Oboril, R. Bishnoi, M. Ebrahimi, and M. B. Tahoori. 2015. Evaluation of hybrid memory technologies using SOT-MRAM for on-chip cache hierarchy. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, 3 (2015), 367–380.
[3]
R. Patel, X. Guo, Q. Guo, E. Ipek, and E. G. Friedman. 2016. Reducing switching latency and energy in STT-MRAM caches with field-assisted writing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24, 1 (2016), 129–138.
[4]
Y. Xu, B. Wu, Z. Wang, Y. Wang, Y. Zhang, and W. Zhao. 2020. Write-efficient STT/SOT hybrid triple-level cell for high-density MRAM. IEEE Transactions on Electron Devices 67, 4 (2020), 1460–1465.
[5]
D. Morris, D. Bromberg, J. Zhu, and L. Pileggi. 2012. mLogic: Ultra-low voltage non-volatile logic circuits using STT-MTJ devices. DAC Design Automation Conference 2012, 486–491.
[6]
S. Motaman, M. N. I. Khan, and S. Ghosh. 2018. Novel application of spintronics in computing, sensing, storage and cybersecurity. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE’18), 125–130
[7]
M. Tehranipoor and C. Wang. 2012. Introduction to Hardware Security and Trust [M]. Springer, New York, 65–102.
[8]
S. Devadas, E. Suh, S. Paral, R. Sowell, T. Ziola, and V. Khandelwal. 2008. Design and implementation of PUF-Based “Unclonable” RFID ICs for anti-counterfeiting and security applications. In IEEE Int. Conf. on RFID, 58–64.
[9]
G. E. Suh and S. Devadas. 2007. Physical unclonable functions for device authentication and secret key generation. In Design Automation Conf., 9–14.
[10]
Z. Liang, M. G. Mankalale, J. Hu, Z. Zhao, J. Wang, and S. S. Sapatnekar. 2018. Performance characterization and majority gate design for MESO-based circuits. IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 4, 2 (2018), 51–59.
[11]
M. G. Mankalale, Z. Liang, Z. Zhao, C. H. Kim, J. Wang, and S. S. Sapatnekar. 2017. CoMET: Composite-input magnetoelectric- based logic technology. IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 3 (2017), 27–36.
[12]
D. Bromberg. 2014. Current-driven magnetic devices for non-volatile logic and memory [Ph.D. dissertation]. Carnegie Mellon University.
[13]
M. Bhargava, C. Cakir, and K. Mai. 2012. Reliability enhancement of bi-stable PUFs in 65 nm bulk CMOS. In Proc. IEEE Symp. Hardw.-Oriented Secur. Trust, 25–30.
[14]
M. Bhargava and K. Mai. 2013. A high reliability PUF using hot carrier injection based response reinforcement. In Proc. 15th Int. Workshop Crypotograph. Hardw. Embedded Syst. 90–106.
[15]
S. V . Kumar, C. H. Kim, and S. S. Sapatnekar. 2006. Impact of NBTI on SRAM read stability and design for reliability. In Proc. IEEE 7th Int. Symp. Quality Electron. Design, Santa Clara (ISQED’06), CA, USA, Mar. 2006. 210–218.
[16]
L. Zhang, X. Fong, C. Chang, Z. H. Kong, and K. Roy. 2015. Highly reliable spin-transfer torque magnetic RAM-Based physical unclonable function with multi-response-bits per cell. IEEE Transactions on Information Forensics and Security 10, 8 (2015), 1630–1642.
[17]
Y . Dodis, L. Reyzin, and A. Smith. 2004. Fuzzy extractors: How to generate strong keys from biometrics and other noisy data. In Proc. International Conference on the Theory and Applications of Cryptographic Techniques (EUROCRYPT’04), Interlaken, Switzerland, May 2004. 523–540.
[18]
C. Bösch, J. Guajardo, A. R. Sadeghi, J. Shokrollahi, and P . Tuyls. 2008. Efficient helper data key extractor on FPGAs. In Proc. 10th Int. Workshop Cryptograph. Hardw. Embedded Syst. (CHES’08), Washington, DC, USA. 181–197.
[19]
Y. Zheng, M. S. Hashemian, and S. Bhunia. 2013. RESP: A robust physical unclonable function retrofitted into embedded SRAM array. In Proc. 50th ACM/EDAC/IEEE Design Autom. Conf. (DAC’13), Austin, TX, USA. 1–9.
[20]
Kursawe A. Sadeghi, D. Schellekens, B. Skoric, and P. Tuyls. 2009. Reconfigurable physical unclonable functions–Enabling technology for tamper-resistant storage. In Proc. 50th ACM/EDAC/IEEE Design Autom. Conf. (DAC’13), Austin, TX, USA. 22–29.
[21]
L. Zhang, Z. H. Kong, and C.-H. Chang. 2013. PCKGen: A phase change memory based cryptographic key generator. In Proc. IEEE Int. Symp. Circuits Syst (ISCAS’13), Beijing, China. 1444–1447.
[22]
A. Iyengar, K. Ramclam, and S. Ghosh. 2014. DWM-PUF: A low-overhead, memory-based security primitive. In 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST’14), 154–159.
[23]
P. Simons, E. van der Sluis, and V. van der Leest. 2012. Buskeeper PUFs, a promising alternative to D flip-flop PUFs. In Proc. IEEE Int. Symp. Hardw. Oriented Secur. Trust (HOST’12), 7–12.
[24]
M. T. Rahman, F. Rahman, D. Forte, and M. Tehranipoor. 2016. An aging-resistant RO-PUF for reliable key generation. IEEE Transactions on Emerging Topics in Computing 4, 3 (2016), 335–348.
[25]
A. Vijayakumar and S. Kundu. 2015. A novel modeling attack resistant PUF design based on non-linear voltage transfer characteristics. In Proc. Design, Automat. Test Eur. Conf. Exhibit. (DATE’15), 653–658.
[26]
E. Dubrova, O. Näslund, B. Degen, A. Gawell, and Y. Yu. 2019. CRC-PUF: A machine learning attack resistant lightweight PUF construction. In 2019 IEEE European Symposium on Security and Privacy Workshops (EuroS & PW’19), 264–271.
[27]
J. Li, P. Ndai, A. Goel, S. Salahuddin, and K. Roy. 2010. Design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18, 12 (2010), 1710–1723.
[28]
X. Fong, S. H. Choday, and K. Roy. 2012. Bit-cell level optimization for non-volatile memories using magnetic tunnel junctions and spin-transfer torque switching. IEEE Transactions on Nanotechnology 11, 1 (2012), 172–181.
[29]
H. Maehara, K. Nishimura, Y. Nagamine, K. Tsunekawa, T. Seki, H. Kubota, A. Fukushima, K. Yakushiji, K. Ando, and S. Yuasa. 2011. Tunnel magnetoresistance above 170 \(\%\) and resistance-area product of 1 \(\Omega \cdot \mu {m^2}\) attained by insitu annealing of ultra-thin MgO tunnel barrier. Applied Physics Express 4, 3 (2011), 033002.
[30]
E. I. Vatajelu, G. Di Natale, M. Indaco, and P. Prinetto. 2015. STT MRAM-based PUFs. In 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE’15), 872–875.
[31]
N. N. Mojumder and K. Roy. 2012. Proposal for switching current reduction using reference layer with tilted magnetic anisotropy in magnetic tunnel junctions for spin-transfer torque (STT) MRAM. IEEE Transactions on Electron Devices 59, 11 (2012), 3054–3060.
[32]
R. Ma, S. Holst, X. Wen, A. Yan, and H. Xu. 2019. STAHL: A novel scan-test-aware hardened latch design. In 2019 IEEE European Test Symposium (ETS’19), Baden-Baden, Germany, 1–6.
[33]
M. Kumngern. 2013. Absolute value circuit for biological signal processing applications. In 2013 4th International Conference on Intelligent Systems, Modelling and Simulation, 601–604.
[34]
M. Elaakhdar, I. Adly, and H. Ragai. 2018. High performance time-continuous differential sense amplifier in time domain sensing with 28 nm technology for automotive applications. In 2018 International Conference on Computing, Electronics & Communications Engineering (iCCECE’18), 262–265.
[35]
K. Kim. 2008. Future memory technology: Challenges and opportunities. In Proc. IEEE Int. Symp. VLSI Technol. Syst. Appl. 5–9.
[36]
A. Pirovano, A. Redaelli, F. Pellizzer, F. Ottogalli, M. Tosi, D. Ielmini, A. L. Lacaita, and R. Bez. 2004. Reliability study of phase-change nonvolatile memories. IEEE Transactions on Device and Materials Reliability 4, 3 (2004), 422–427.
[37]
S. A. Wolf, J. Lu, M. R. Stan, E. Chen, and D. M. Treger. 2010. The promise of nanomagnetics and spintronics for future logic and universal memory. Proceedings of the IEEE 98, 12 (2010), 2155–2168.
[38]
S. Ben Dodo, R. Bishnoi, and M. B. Tahoori. 2020. Secure STT-MRAM bit-cell design resilient to differential power analysis attacks. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28, 1 (2020), 263–272.
[39]
M. Cortez, S. Hamdioui, V. van der Leest, R. Maes, and G.-J. Schrijen. 2013. Adapting voltage ramp-up time for temperature noise reduction on memory-based PUFs. In Proc. IEEE Int. Symp. Hardw.-Oriented Secur. Trust, 35–40.
[40]
L. Yu, X. Wang, F. Rahman, and M. Tehranipoor. 2020. Interconnect-based PUF with signature uniqueness enhancement. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28, 2 (2020), 339–352.
[42]
ITC99 Benchmark. [n.d.]. Retrieved October 17, 2020, from http://www.cerc.utexas.edu/itc99-benchmarks/bench.html.
[43]
Gaisler Benchmark. [n.d.]. Retrieved October 17, 2017, from http://www.gaisler.com/index.php/downloads/leongrlib.
[44]
Opensparc Benchmark. [n.d.]. Retrieved October 17, 2017, from http://www.oracle.com/technetwork/systems/opensparc.
[45]
ISCAS Benchmark. [n.d.]. Retrieved October 17, 2017, from http://web.eecs.umich.edu/jhayes/iscas.restore/benchmark.html.
[46]
Daniel H. Morris. 2012. mLogic: Nonvolatile pulsed-current logic and memory circuits. [J]. Dissertations & Theses - Gradworks, 2012.
[47]
B. Wu, Y. Cheng, J. Yang, A. Todri-Sanial, and W. Zhao. 2016. Temperature impact analysis and access reliability enhancement for 1T1MTJ STT-RAM. IEEE Transactions on Reliability 65, 4 (2016), 1755–1768.
[48]
H. Zhao et al. 2012. Spin-transfer torque switching above ambient temperature. IEEE Magnetics Letters 3 (2012), Art. ID 3000304.
[49]
STT-mCell Model Manual. 2014. Retrieved October 2, 2019, from https://nanohub.org/resources/21633/download.
[50]
Z. Wang et al. 2018. Current mirror array: A novel circuit topology for combining physical unclonable function and machine learning. IEEE Transactions on Circuits and Systems I: Regular Papers 65, 4 (2018), 1314–1326.
[51]
E. I. Vatajelu, G. Di Natale, M. Barbareschi, L. Torres, M. Indaco, and P. Prinetto. 2016. STT-MRAM-based PUF architecture exploiting magnetic tunnel junction fabrication-induced variability. ACM Journal on Emerging Technologies in Computing Systems 13, 1 (2016), 5:1–5:21.
[52]
Y . Su, J. Holleman, and B. P. Otis. 2008. A digital 1.6 pJ/bit chip identification circuit using process variations. IEEE Journal on Solid-State Circuits 43, 1 (2008), 69–77.
[53]
J. Li and M. Seok. 2016. Ultra-compact and robust physically unclonable function based on voltage-compensated proportional-to-absolute-temperature voltage generators. IEEE Journal on Solid-State Circuits 51, 9 (2016), 2192–2202.
[54]
A. Alvarez, W. Zhao, and M. Alioto. 2015. 14.3 15fJ/b static physically unclonable functions for secure chip identification with <2 \(\%\) native bit instability and 140 \(\times\) Inter/Intra PUF hamming distance separation in 65nm. In 2015 IEEE International Solid-State Circuits Conference (ISSCC’15), Digest of Technical Papers, 1–3.
[55]
P. Simons, E. van der Sluis, and V. van der Leest. 2012. Buskeeper PUFs, a promising alternative to D flip-flop PUFs. In Proc. IEEE Int. Symp. Hardw.-Oriented Secur. Trust (HOST’12), 7–12.
[56]
U. Rhrmair and J. Slter. 2014. PUF modeling attacks: An introduction and overview. In 2014 Design, Automation Test in Europe Conference Exhibition (DATE’14), 1–6.
[57]
J. Delvaux and I. Verbauwhede. 2014. Fault injection modeling attacks on 65nm arbiter and RO sum PUFs via environmental changes. IEEE Transactions on Circuits \(\&#x0026;\) Systems I Regular Papers 61, 6 (2014), 1701–1713.
[58]
G. Shi and J. Ru. 2016. Research on classification of memory attack. In Proc. 2nd Workshop Adv. Res. Technol. Ind. Appl. (WARTIA’16). Paris, France: Atlantis Press, 392–397.
[59]
J. Barrett, R. Colbeck, and A. Kent. 2013. Memory attacks on device-independent quantum cryptography. Physical Review Letters 110, 1 (2013), 1–6.
[60]
Xu, Xiaolin and W. P. Burleson. 2014. Hybrid side-channel/machine-learning attacks on PUFs: A new threat? In Design Automation and Test in Europe (DATE’14). 1–6.

Cited By

View all
  • (2024)Instance-level Adversarial Source-free Domain Adaptive Person Re-identificationACM Transactions on Multimedia Computing, Communications, and Applications10.1145/364990020:7(1-22)Online publication date: 25-Apr-2024
  • (2024)DMA: Dual Modality-Aware Alignment for Visible-Infrared Person Re-IdentificationIEEE Transactions on Information Forensics and Security10.1109/TIFS.2024.335240819(2696-2708)Online publication date: 10-Jan-2024
  • (2024)Era of Sentinel Tech: Charting Hardware Security Landscapes Through Post-Silicon Innovation, Threat Mitigation and Future TrajectoriesIEEE Access10.1109/ACCESS.2024.340062412(68061-68108)Online publication date: 2024
  • Show More Cited By

Index Terms

  1. All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits

      Recommendations

      Comments

      Information & Contributors

      Information

      Published In

      cover image ACM Journal on Emerging Technologies in Computing Systems
      ACM Journal on Emerging Technologies in Computing Systems  Volume 18, Issue 4
      October 2022
      429 pages
      ISSN:1550-4832
      EISSN:1550-4840
      DOI:10.1145/3563906
      • Editor:
      • Ramesh Karri
      Issue’s Table of Contents

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Journal Family

      Publication History

      Published: 13 October 2022
      Online AM: 25 March 2022
      Accepted: 11 February 2022
      Revised: 30 November 2021
      Received: 22 May 2021
      Published in�JETC�Volume 18, Issue 4

      Permissions

      Request permissions for this article.

      Check for updates

      Author Tags

      1. Spin-Transfer Torque magnetic Cell (STT-mCell)
      2. hardware security
      3. physical unclonable function (PUF)
      4. automatic write-back
      5. signature improvement

      Qualifiers

      • Research-article
      • Refereed

      Funding Sources

      • Beijing Natural Science Foundation
      • Science, Technology and Innovation Commission of Shenzhen Municipality

      Contributors

      Other Metrics

      Bibliometrics & Citations

      Bibliometrics

      Article Metrics

      • Downloads (Last 12 months)115
      • Downloads (Last 6 weeks)18
      Reflects downloads up to 16 Oct 2024

      Other Metrics

      Citations

      Cited By

      View all
      • (2024)Instance-level Adversarial Source-free Domain Adaptive Person Re-identificationACM Transactions on Multimedia Computing, Communications, and Applications10.1145/364990020:7(1-22)Online publication date: 25-Apr-2024
      • (2024)DMA: Dual Modality-Aware Alignment for Visible-Infrared Person Re-IdentificationIEEE Transactions on Information Forensics and Security10.1109/TIFS.2024.335240819(2696-2708)Online publication date: 10-Jan-2024
      • (2024)Era of Sentinel Tech: Charting Hardware Security Landscapes Through Post-Silicon Innovation, Threat Mitigation and Future TrajectoriesIEEE Access10.1109/ACCESS.2024.340062412(68061-68108)Online publication date: 2024
      • (2024)Design of small volume and low power consumption logic gates based on 4-terminal multilevel magnetic cellJournal of Magnetism and Magnetic Materials10.1016/j.jmmm.2023.171516597(171516)Online publication date: May-2024
      • (2023)An Ultra-Compact Pure Magnetic Arbiter PUF With High Reliability and Low Power ConsumptionIEEE Transactions on Nanotechnology10.1109/TNANO.2023.329248122(449-456)Online publication date: 1-Jan-2023
      • (2023)OSAP‐LossCAAI Transactions on Intelligence Technology10.1049/cit2.121518:4(1191-1212)Online publication date: 28-Mar-2023

      View Options

      Get Access

      Login options

      Full Access

      View options

      PDF

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader

      Full Text

      View this article in Full Text.

      Full Text

      HTML Format

      View this article in HTML Format.

      HTML Format

      Media

      Figures

      Other

      Tables

      Share

      Share

      Share this Publication link

      Share on social media