Article

Self-correcting LRU replacement policies

Authors:

Michel DuboisAuthors Info & Claims

CF '04: Proceedings of the 1st conference on Computing frontiers

Pages 181 - 191

https://doi.org/10.1145/977091.977117

Published: 14 April 2004 Publication History

Abstract

L1 caches must be fast and have a good hit rate at the same time. To be fast, they must remain small. To have a good hit rate, they must be set-associative. With wider associativity the replacement algorithm becomes critical. The wide performance gap between OPT, the optimum off-line algorithm, and LRU suggests that LRU still makes too many mistakes. One way to improve L1 cache behavior is to manage actively the replacement policy to correct these mistakes on the fly.We introduce Self-correcting LRU (SCLRU) which is based on LRU augmented with a feedback loop to constantly monitor and correct replacement mistakes. It relies on several mechanisms to detect, predict, and correct bad replacement decisions. We identify three types of mistakes made by LRU and associate them with memory-access instructions. Our goal is to prevent a mistake to occur more than once. Based on evaluations using a set of seven SPEC95 benchmarks, we show that our approach achieves significant and reliable miss rate improvements, sometimes close to that of OPT, for 2-way and 4-way L1 caches and can do this at a low implementation cost and without affecting the hit cycle time.

References

[1]

L. A. Barroso, K. Gharachorloo and E. Bugnion. Memory System Characterization of Commercial Workloads. In Proceedings of the 25th International Symposium on Computer Architecture, pp. 3--14, June 1998.

Digital Library

[2]

L. Belady. A Study of Replacement Algorithms for a Virtual-Storage Computer. In IBM Systems Journal, v. 5, no. 2, pp. 78--101, 1966.

[3]

D. Burger, Doug and T. M. Austin,. The SimpleScalar Tool Set, Version 2. University of Wisconsin-Madison Computer Science Department, TN-1342, 1997.

[4]

A. Gonz�lez, C. Aliagas and M. Valero. A Data Cache with Multiple Caching Strategies tuned to Different Types of Locality. In Proceedings of the 9th ACM international conference on Supercomputing, pp. 338--347, July 1995.

Digital Library

[5]

J. Jalminger and P. Stenstrom. A Novel Approach to Cache Reuse Prediction. In Proceedings of 32nd International Parallel Processing Conference (ICPP-2003). Oct. 2003.

[6]

T. L. Johnson, D. A. Connors, M. C. Merten, and W. W. Hwu. Run-Time Cache Bypassing. In IEEE Transactions on Computers, Vol. 48, No. 12, pp. 1338--1354, December 1999.

Digital Library

[7]

T. L. Johnson and W. Hwu. Run-time Adaptive Cache Hierarchy Management via Reference Analysis. In Proceedings of the 24th International Symposium on Computer Architecture, pp. 315--326, June 1997.

Digital Library

[8]

N.P. Jouppi. Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associativ Cache and Prefetch Buffers. In Proceedings of the 17th International Symposium on Computer Architecture, pp. 364--373, May 1990.

Digital Library

[9]

M. Karlsson and E. Hagersten, "Timestamp-based Selective Cache Allocation", High Performance Memory Systems, edited by H. Hadimiouglu, D. Kaeli, J. Kuskin, A. Nanda, and J. Torrellas, Springer-Verlag, 2003.

[10]

M. K�mpe and F. Dahlgren. Exploration of the Spatial Locality on Emerging Applications and the Consequences for Cache Performance. In Proceedings of the 14th International Parallel and Distributed Computing Symposium, pp. 163--170, May 2000.

Digital Library

[11]

A-C Lai, C. Fide, and B. Falsafi. Dead-block Prediction and Dead-block Correlating Prefetchers. In Proceedings of the 28th International Symposium on Computer Architecture, pp. 144--154, July 2001.

Digital Library

[12]

R. L. Mattson, J. Gecsei, D. R. Slutz and I. L. Traiger. Evaluation Techniques for Storage Hierarchies. In IBM Systems Journal, vol. 9, pp. 77--117, 1970.

Digital Library

[13]

V. Milutinovic, B. Markovic, M. Tomasevic, and M. Tremblay. The Split Temporal/Spatial Cache: Initial Performance analysis. In Proceedings of SCIzzL-5, pp. 63--70, March 1996.

[14]

M. Prvulovic, D. Marinov, Z. Dimitrijevic, and V. Milutinovic. Split Temporal/Spatial Cache: A Survey and Reevaluation of Performance, IEEE TCCA Newsletter, pp. 1--10, 1999.

[15]

A. J. Smith. Cache Memories. ACM Computing Surveys, vol. 3, pp. 473--530, September 1982.

Digital Library

[16]

Standard Performance Evaluation Corporation. http://www.spec.org. SPEC 95. August 1995.

[17]

H. S. Stone. High Performance Computer Architecture. Addison-Wesley 1993 (3rd ed.).

[18]

E. S. Tam, J.A. Rivers, V. Srinivasan, G.S. Tyson, and E.S. Davidson. Active Management of Data Caches by Exploiting Reuse Information. In IEEE Transactions on Computers, Vol. 48, No. 11, pp. 1244--1259, November 1999.

Digital Library

[19]

Gary Tyson, Matthew Farrens, John Matthews, Andrew R Pleszkun. A Modified Approach to Data Cache Management. In Proceedings of MICRO-28, pp. 93--103, November 1995.

Digital Library

[20]

Wayne A. Wong and Jean-Loup Baer. Modified LRU Policies for Improving Second-level Cache Behavior. In Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, pp. 49--60, January 2000.

Cited By

Barbhuiya NDas PRoy B(2024)Cache Memory and On-Chip Cache Architecture: A SurveyAdvanced Computing, Machine Learning, Robotics and Internet Technologies10.1007/978-3-031-47221-3_12(126-138)Online publication date: 16-Apr-2024
https://doi.org/10.1007/978-3-031-47221-3_12
Heo TWang YCui WHuh JZhang L(2022)Adaptive Page Migration Policy With Huge Pages in Tiered Memory SystemsIEEE Transactions on Computers10.1109/TC.2020.303668671:1(53-68)Online publication date: 1-Jan-2022
https://doi.org/10.1109/TC.2020.3036686
Titinchi AHalasa N(2019)FPGA implementation of simplified Fuzzy LRU replacement algorithm2019 16th International Multi-Conference on Systems, Signals & Devices (SSD)10.1109/SSD.2019.8893205(657-662)Online publication date: Mar-2019
https://doi.org/10.1109/SSD.2019.8893205
Show More Cited By

Index Terms

Self-correcting LRU replacement policies
1. Applied computing
  1. Computers in other domains
    1. Personal computers and PC applications
      1. Microcomputers
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

Recommendations

Enhancing LRU replacement via phantom associativity
INTERACT '12: Proceedings of the 2012 16th Workshop on Interaction between Compilers and Computer Architectures (INTERACT)

In this paper, we propose a novel cache design, Phantom Associative Cache (PAC), that alleviates cache thrashing in L2 caches by keeping the in-cache data blocks for a longer time period. To realize PAC, we introduce the concept of phantom lines. A ...
Dynamically Configuring LRU Replacement Policy in Redis
MEMSYS '20: Proceedings of the International Symposium on Memory Systems

To reduce the latency of accessing backend servers, today’s web services usually adopt in-memory key-value stores in the front end which cache the frequently accessed objects. Memcached and Redis are two most popular key-value cache systems. Due to the ...
Simple penalty-sensitive replacement policies for caches
CF '06: Proceedings of the 3rd conference on Computing frontiers

Classic cache replacement policies assume that miss costs are uniform. However, the correlation between miss rate and cache performance is not as straightforward as it used to be. Ultimately, the true cost measure of a miss should be the penalty, i.e. ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

CF '04: Proceedings of the 1st conference on Computing frontiers

April 2004

522 pages

ISBN:1581137419

DOI:10.1145/977091

General Chair:
Stamatis Vassiliadis
Delft University of Technology, The Netherlands
,
Program Chairs:
Jean-Luc Gaudiot
University of California at Irvine, USA
,
Vincenzo Piuri
University of Milan, Italy

Copyright � 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 14 April 2004

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

CF04

Sponsor:

CF04: Computing Frontiers Conference

April 14 - 16, 2004

Ischia, Italy

Acceptance Rates

Overall Acceptance Rate 273 of 785 submissions, 35%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

24
Total Citations
View Citations
794
Total Downloads

Downloads (Last 12 months)4
Downloads (Last 6 weeks)1

Reflects downloads up to 17 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

Barbhuiya NDas PRoy B(2024)Cache Memory and On-Chip Cache Architecture: A SurveyAdvanced Computing, Machine Learning, Robotics and Internet Technologies10.1007/978-3-031-47221-3_12(126-138)Online publication date: 16-Apr-2024
https://doi.org/10.1007/978-3-031-47221-3_12
Heo TWang YCui WHuh JZhang L(2022)Adaptive Page Migration Policy With Huge Pages in Tiered Memory SystemsIEEE Transactions on Computers10.1109/TC.2020.303668671:1(53-68)Online publication date: 1-Jan-2022
https://doi.org/10.1109/TC.2020.3036686
Titinchi AHalasa N(2019)FPGA implementation of simplified Fuzzy LRU replacement algorithm2019 16th International Multi-Conference on Systems, Signals & Devices (SSD)10.1109/SSD.2019.8893205(657-662)Online publication date: Mar-2019
https://doi.org/10.1109/SSD.2019.8893205
Yang ZWang YBhamini JTan CMi N(2018)EADCluster Computing10.5555/3287988.328800521:3(1561-1579)Online publication date: 1-Sep-2018
https://dl.acm.org/doi/10.5555/3287988.3288005
Manivannan MPeric�s MPapaefstathiou VStenstr�m P(2018)Global Dead-Block Management for Task-Parallel ProgramsACM Transactions on Architecture and Code Optimization10.1145/323433715:3(1-25)Online publication date: 4-Sep-2018
https://dl.acm.org/doi/10.1145/3234337
Yang ZWang YBhamini JTan CMi N(2018)EAD: elasticity aware deduplication manager for datacenters with multi-tier storage systemsCluster Computing10.1007/s10586-018-2141-z21:3(1561-1579)Online publication date: 7-Mar-2018
https://doi.org/10.1007/s10586-018-2141-z
Tai JLiu DYang ZZhu XLo JMi N(2017)Improving Flash Resource Utilization at Minimal Management Cost in Virtualized Flash-Based Storage SystemsIEEE Transactions on Cloud Computing10.1109/TCC.2015.24248865:3(537-549)Online publication date: 1-Jul-2017
https://doi.org/10.1109/TCC.2015.2424886
Mittal S(2016)A Survey of Cache Bypassing TechniquesJournal of Low Power Electronics and Applications10.3390/jlpea60200056:2(5)Online publication date: 28-Apr-2016
https://doi.org/10.3390/jlpea6020005
Manivannan MPapaefstathiou VPericas MStenstrom P(2016)RADAR: Runtime-assisted dead region management for last-level caches2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2016.7446101(644-656)Online publication date: Mar-2016
https://doi.org/10.1109/HPCA.2016.7446101
Panda PPatil GRaveendran B(2016)A survey on replacement strategies in cache memory for embedded systems2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)10.1109/DISCOVER.2016.7806218(12-17)Online publication date: Aug-2016
https://doi.org/10.1109/DISCOVER.2016.7806218
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents