With 6 individual classifiers on a single chip and a rule set of size IK, our design sustains a throughput of 400 Gbps for minimum size (40 bytes) packets and ...
Abstract—Packet classification is a network kernel function that has been widely researched over the past decade. How- ever, most previous work has only ...
With 6 individual classifiers on a single chip and a rule set of size IK, our design sustains a throughput of 400 Gbps for minimum size (40 bytes) packets and ...
Click here for the complete list of publications of all Labs under Prof. Viktor K. Prasanna. FPGA/PARALLEL COMPUTING LAB Led by Dr. Viktor K. Prasanna
This paper presents an approach for harnessing modern Field Programmable Gate Array. (FPGA) devices, which are a natural technology for implementing the ...
The Packet Classification Engine (PCE) is configured to evaluate Ethernet packets based on the source IP address, destination IP address, source port, ...
Optimizing many-field packet classification on FPGA, multi-core general purpose processor, and GPU ... 400 Gbps energy-efficient multi-field packet classification ...
400 Gbps energy-efficient multi-field packet classification on FPGA. ... Scalable Many-Field Packet Classification on Multi-core Processors. SBAC-PAD 2013 ...
We propose and examine a unique parallel hardware architecture for hash-based exact match classification of multiple packets in each clock cycle.
This paper presents a low power architecture for a high speed packet classifier which can meet OC-768 line rate. The architecture consists of an adaptive ...