Sep 26, 2017 · A digital fractional-N phase-locked loop (PLL) is presented. It achieves 137- and 142-fs rms jitter integrating from 10 kHz to 10 MHz and from 1 kHz to 10 MHz, ...

A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration · Chih-Wei ...

Abstract—A digital fractional-N phase-locked loop (PLL) is presented. It achieves 137- and 142-fs rms jitter integrating from.

A low-power clocking solution is presented based on fractional-N highly digital LC-phase-locked loop (PLL) and sub-sampled ring PLL targeting multi-standard ...

A 14-nm 0.14-psrmsFractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration. CW Yao, R ...

This work presents a 6-GHz low-jitter and high figure-of-merit (FoM) fractional- $N$ phase-locked loop (PLL). It uses a digital-to-time converter ...

This work presents a low-spur and low-jitter fractional-based digital phase-locked loop (PLL) that achieves high-linearity.

Yao et al., “A 14-nm 0.14-ps. rms. frac-. tional-N digital PLL with a 0.2-ps resolu-. tion ADC-assisted coarse/fine-conversion. chopping TDC and TDC ...

Aug 14, 2024 · ... N digital PLL with an ADC-assisted TDC, significantly improving time resolution. ... A 14-nm 0.14-psrms Fractional-N digital PLL with a 0.2-ps ...

Compared with traditional PLLs, a charge pump phase-locked loop (CP-PLL) provides a highly robust electronic system with a stable reference frequency source. A ...