We develop our model which guarantees that the minimum and maximum delay values it computes are guaranteed to bound the corresponding delay values in silicon.

We develop our model which guarantees that the minimum and maximum delay values it computes are guaranteed to bound the corresponding delay values in silicon.

Prasanjeet Das, Sandeep K. Gupta: Gate delay modeling for pre- and post-silicon timing related tasks for ultra-low power CMOS circuits. ICCD 2013: 227-234.

Abstract：Gate delay modeling for pre- and post-silicon timing related tasks for ultra-low power CMOS circuits.

Delay models are foundations of most of pre- and post-silicon timing related tasks [23]. It is imperative for a gate's delay model to accurately represent ...

Gate delay modeling for pre-and post-silicon timing related tasks for ultra-low power CMOS circuits. P Das, SK Gupta. 2013 IEEE 31st International Conference ...

We present a new model to capture the delay phenomena associated with simultaneous to-controlling transitions. The proposed delay model accurately captures ...

Prasanjeet Das, Sandeep K. Gupta: Gate delay modeling for pre- and post-silicon timing related tasks for ultra-low power CMOS circuits. ICCD 2013: 227-234.

Gate delay modeling for pre- and post-silicon timing related tasks for ultra-low power CMOS circuits · Conference Paper. October 2013. ·. 12 Reads. ·. 1 ...

In this paper we present an efficient method to detect hardware Trojans under high levels of process variations, by measuring delays for vectors generated.