In this paper, an efficient thread-mapping algorithm is proposed to minimize the cache race condition between threads of multi-core systems.

Abstract—Multi-level hierarchical cache architectures are now being widely used in the design and fabrication of multi and many-core chips.

This study addresses both the security and performance of modern processors equipped with shared caches based on our previous work [16] by introducing a ...

RaceR: A thread mapping algorithm for race reduction in multi-level shared caches ... Joint security and performance improvement in multilevel shared caches.

Apr 14, 2021 · In this section, a thread mapping/remapping algorithm is proposed to jointly to address the performance and security of multilayer shared caches ...

Apr 14, 2021 · Then, a thread-mapping algorithm to detect such race conditions between a group of threads and resolve them as a countermeasure against the ...

Jan 3, 2022 · The proposed attack prolongs the execution time of the victim threads by inducing intentional race conditions in shared memory spaces. Then, a ...

RaceR: A Thread Mapping Algorithm for Race Reduction in Multi-Level Shared Caches. 2019 27th Euromicro International Conference on Parallel, Distributed and ...

We use AKULA to develop and evaluate a variety of different contention-aware scheduling algorithms. We use the rapid evaluation module to test our algorithms on ...

RaceR: A thread mapping algorithm for race reduction in multi-level shared caches ... Joint security and performance improvement in multilevel shared caches.