A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4
MS Lin, CC Tsai, S Li, TC Huang… - … IEEE Symposium on …, 2024 - ieeexplore.ieee.org
This paper presents a die-to-die link with a compute die in 5nm FinFET and a SRAM die in
6nm FinFET, with a face-to-back 3D stacking at a 9μm bond pitch. Modular design that
supports full scalability is demonstrated, achieving a 10.24 Tb/s aggregate bandwidth for
320 Tx lanes and 320 Rx lanes, at a PAM-4 16Gb/s per lane data rate. Each data cluster is
designed with 80 Tx/Rx lanes in a 378μm* 378μm footprint, achieving a bandwidth density
of 17.9 Tb/s/mm2 and an energy efficiency of 0.296 pJ/bit per link.
6nm FinFET, with a face-to-back 3D stacking at a 9μm bond pitch. Modular design that
supports full scalability is demonstrated, achieving a 10.24 Tb/s aggregate bandwidth for
320 Tx lanes and 320 Rx lanes, at a PAM-4 16Gb/s per lane data rate. Each data cluster is
designed with 80 Tx/Rx lanes in a 378μm* 378μm footprint, achieving a bandwidth density
of 17.9 Tb/s/mm2 and an energy efficiency of 0.296 pJ/bit per link.
[PDF][PDF] A 0.296 pJ/bit 17.9 Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-pitch 3D Package Achieving
MS Lin, CC Tsai, S Li, TC Huang, WH Huang, K Huang… - vlsi24.mapyourshow.com
This paper presents a die-to-die link with a compute die in 5nm FinFET and a SRAM die in
6nm FinFET, with a face-to-back 3D stacking at a 9µm bond pitch. Modular design that
supports full scalability is demonstrated, achieving a 10.24 Tb/s aggregate bandwidth for
320 Tx lanes and 320 Rx lanes, at a PAM-4 16Gb/s per lane data rate. Each data cluster is
designed with 80 Tx/Rx lanes in a 378µm* 378µm footprint, achieving a bandwidth density
of 17.9 Tb/s/mm2 and an energy efficiency of 0.296 pJ/bit per link.
6nm FinFET, with a face-to-back 3D stacking at a 9µm bond pitch. Modular design that
supports full scalability is demonstrated, achieving a 10.24 Tb/s aggregate bandwidth for
320 Tx lanes and 320 Rx lanes, at a PAM-4 16Gb/s per lane data rate. Each data cluster is
designed with 80 Tx/Rx lanes in a 378µm* 378µm footprint, achieving a bandwidth density
of 17.9 Tb/s/mm2 and an energy efficiency of 0.296 pJ/bit per link.
