"A Unified Approach for Full Chip Statistical Timing and Leakage Analysis ..."

Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Amit Goel (2008)

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DOI: 10.1109/TCAD.2008.927671

access: closed

type: Journal Article

metadata version: 2020-09-24

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Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Amit Goel:
A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(10): 1812-1825 (2008)

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