research-article

Software partitioning of hardware transactions

Authors:

Lingxiang Xiang,

Michael L. ScottAuthors Info & Claims

ACM SIGPLAN Notices, Volume 50, Issue 8

Pages 76 - 86

https://doi.org/10.1145/2858788.2688506

Published: 24 January 2015 Publication History

Abstract

Best-effort hardware transactional memory (HTM) allows complex operations to execute atomically and in parallel, so long as hardware buffers do not overflow, and conflicts are not encountered with concurrent operations. We describe a programming technique and compiler support to reduce both overflow and conflict rates by partitioning common operations into read-mostly (planning) and write-mostly (completion) operations, which then execute separately. The completion operation remains transactional; planning can often occur in ordinary code. High-level (semantic) atomicity for the overall operation is ensured by passing an application-specific validator object between planning and completion. Transparent composition of partitioned operations is made possible through fully-automated compiler support, which migrates all planning operations out of the parent transaction while respecting all program data flow and dependences. For both micro- and macro-benchmarks, experiments on IBM z-Series and Intel Haswell machines demonstrate that partitioning can lead to dramatically lower abort rates and higher scalability.

References

[1]

Y. Afek, H. Avni, and N. Shavit. Towards consistency oblivious programming. In Proc. of the 15th Intl. Conf. on Principles of Distributed Systems (OPODIS), Toulouse, France, Dec. 2011.

Digital Library

[2]

H. Avni and B. Kuszmaul. Improve HTM scaling with consistency-oblivious programming. In 9th SIGPLAN Wkshp. on Transactional Computing (TRANSACT), Salt Lake City, UT, Mar. 2014.

[3]

H. Avni and A. Suissa. TM-pure in GCC compiler allows consistency oblivious composition. In Joint Euro-TM/MEDIAN Wkshp. on Dependable Multicore and Transactional Memory Systems (DMTM), Vienna Austria, Jan. 2014.

[4]

N. G. Bronson, J. Casper, H. Chafi, and K. Olukotun. Transactional predication: High-performance concurrent sets and maps for STM. In 29th ACM Symp. on Principles of Distributed Computing (PODC), Zurich, Switzerland, July 2010.

Digital Library

[5]

H. W. Cain, M. M. Michael, B. Frey, C. May, D. Williams, and H. Le. Robust architectural support for transactional memory in the Power architecture. In 40th Intl. Symp. on Computer Architecture (ISCA), Tel Aviv, Israel, June 2013.

Digital Library

[6]

C. Click Jr. And now some hardware transactional memory comments. Author’s Blog, Azul Systems, Feb. 2009. www.azulsystems.com/blog/cliff/2009- 02-25-and-now-some-hardware-transactional-memory-comments.

[7]

D. Dice, Y. Lev, M. Moir, and D. Nussbaum. Early experience with a commercial hardware transactional memory implementation. In 14th Intl. Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Washington, DC, Mar. 2009.

Digital Library

[8]

D. Dice, O. Shalev, and N. Shavit. Transactional Locking II. In 20th Intl. Conf. on Distributed Computing (DISC), Stockholm, Sweden, Sept. 2006.

Digital Library

[9]

P. Felber, V. Gramoli, and R. Guerraoui. Elastic transactions. In 23rd Intl. Conf. on Distributed Computing (DISC), Elche/Elx, Spain, Sept. 2009.

Digital Library

[10]

G. Golan-Gueta, G. Ramalingam, M. Sagiv, and E. Yahav. Concurrent libraries with Foresight. In 34th SIGPLAN Conf. on Programming Language Design and Implementation (PLDI), Seattle, WA, June 2013.

Digital Library

[11]

M. Herlihy and E. Koskinen. Transactional boosting: a methodology for highlyconcurrent transactional objects. In 13th SIGPLAN Symp. on Principles and Practice of Parallel Programming (PPoPP), Salt Lake City, UT, Feb. 2008.

Digital Library

[12]

M. Herlihy, V. Luchangco, M. Moir, and W. N. Scherer, III. Software transactional memory for dynamic-sized data structures. In 22nd ACM Symp. on Principles of Distributed Computing (PODC), Boston, MA, July 2003.

Digital Library

[13]

M. Herlihy and J. E. B. Moss. Transactional memory: Architectural support for lock-free data structures. In 20th Intl. Symp. on Computer Architecture (ISCA), San Diego, CA, May 1993.

Digital Library

[14]

C. Jacobi, T. Slegel, and D. Greiner. Transactional memory architecture and implementation for IBM System z. In 45th Intl. Symp. on Microarchitecture (MICRO), Vancouver, BC, Canada, Dec. 2012.

Digital Library

[15]

C. Lattner and V. Adve. Automatic pool allocation: Improving performance by controlling data structure layout in the heap. In 26th SIGPLAN Conf. on Programming Language Design and Implementation (PLDI), Chicago, IL, June 2005.

Digital Library

[16]

Y. Lev and J.-W. Maessen. Split hardware transactions: True nesting of transactions using best-effort hardware transactional memory. In 13th SIGPLAN Symp. on Principles and Practice of Parallel Programming (PPoPP), Salt Lake City, UT, Feb. 2008.

Digital Library

[17]

M. M. Michael and M. L. Scott. Simple, fast, and practical non-blocking and blocking concurrent queue algorithms. In 15th ACM Symp. on Principles of Distributed Computing (PODC), Philadelphia, PA, May 1996.

Digital Library

[18]

J. E. B. Moss and A. L. Hosking. Nested transactional memory: Model and architecture sketches. Science of Computer Programming, 63(2):186–201, Dec. 2006.

Digital Library

[19]

A. Wang, M. Gaudet, P. Wu, J. N. Amaral, M. Ohmacht, C. Barton, R. Silvera, and M. Michael. Evaluation of Blue Gene/Q hardware support for transactional memories. In 21st Intl. Conf. on Parallel Architectures and Compilation Techniques (PACT), Minneapolis, MN, Sept. 2012.

Digital Library

[20]

L. Xiang and M. L. Scott. MSpec: A design pattern for concurrent data structures. In 7th SIGPLAN Wkshp. on Transactional Computing (TRANSACT), New Orleans, LA, Feb. 2012.

[21]

L. Xiang and M. L. Scott. Compiler aided manual speculation for high performance concurrent data structures. In 18th SIGPLAN Symp. on Principles and Practice of Parallel Programming (PPoPP), Shenzhen, China, Feb. 2013.

Digital Library

[22]

L. Xiang and M. L. Scott. Composable partitioned transactions. In 5th Wkshp. on the Theory of Transactional Memory (WTTM), Jerusalem, Israel, Oct. 2013.

[23]

R. M. Yoo, C. J. Hughes, K. Lai, and R. Rajwar. Performance evaluation of Intel transactional synchronization extensions for high-performance computing. In Intl. Conf. on High Performance Computing, Networking, Storage and Analysis (SC13), Denver, CO, Nov. 2013.

Digital Library

Cited By

Wu ZLu KWang RZhang W(2020)A survey on optimizations towards best-effort hardware transactional memoryCCF Transactions on High Performance Computing10.1007/s42514-020-00049-2Online publication date: 15-Sep-2020
https://doi.org/10.1007/s42514-020-00049-2
Cerone AGotsman A(2018)Analysing Snapshot IsolationJournal of the ACM10.1145/315239665:2(1-41)Online publication date: 31-Jan-2018
https://dl.acm.org/doi/10.1145/3152396
Siakavaras DNikas KGoumas GKoziris N(2016)Massively Concurrent Red-Black Trees with Hardware Transactional Memory2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)10.1109/PDP.2016.65(127-134)Online publication date: Feb-2016
https://doi.org/10.1109/PDP.2016.65
Show More Cited By

Index Terms

Software partitioning of hardware transactions
1. Computing methodologies
  1. Concurrent computing methodologies
    1. Concurrent programming languages
2. Software and its engineering
  1. Software notations and tools
    1. Compilers
    2. General programming languages
      1. Language types
        Concurrent programming languages

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Information

Published In

cover image ACM SIGPLAN Notices

ACM SIGPLAN Notices Volume 50, Issue 8

PPoPP '15

August 2015

290 pages

ISSN:0362-1340

EISSN:1558-1160

DOI:10.1145/2858788

Editor:
Andy Gill
University of Kansas, Lawrence, KS

Issue’s Table of Contents

PPoPP 2015: Proceedings of the 20th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
January 2015
290 pages
ISBN:9781450332057
DOI:10.1145/2688500
General Chair:
Albert Cohen
INRIA, France
,
Program Chair:
David Grove
IBM Research, USA

Copyright � 2015 ACM.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 24 January 2015

Published in�SIGPLAN�Volume 50, Issue 8

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Cited By

Wu ZLu KWang RZhang W(2020)A survey on optimizations towards best-effort hardware transactional memoryCCF Transactions on High Performance Computing10.1007/s42514-020-00049-2Online publication date: 15-Sep-2020
https://doi.org/10.1007/s42514-020-00049-2
Cerone AGotsman A(2018)Analysing Snapshot IsolationJournal of the ACM10.1145/315239665:2(1-41)Online publication date: 31-Jan-2018
https://dl.acm.org/doi/10.1145/3152396
Siakavaras DNikas KGoumas GKoziris N(2016)Massively Concurrent Red-Black Trees with Hardware Transactional Memory2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)10.1109/PDP.2016.65(127-134)Online publication date: Feb-2016
https://doi.org/10.1109/PDP.2016.65
Hassan APalmieri RRavindran B(2015)Transactional Interference-Less Balanced TreeProceedings of the 29th International Symposium on Distributed Computing - Volume 936310.1007/978-3-662-48653-5_22(325-340)Online publication date: 7-Oct-2015
https://dl.acm.org/doi/10.1007/978-3-662-48653-5_22
Sheng YHassan ASpear M(2023)Separating Mechanism from Policy in STM2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT)10.1109/PACT58117.2023.00031(279-296)Online publication date: 21-Oct-2023
https://doi.org/10.1109/PACT58117.2023.00031
Titos-Gil RFernandez Pascual RRos AAcacio M(2021)DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional MemoryIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2021.3085210(1-1)Online publication date: 2021
https://doi.org/10.1109/TPDS.2021.3085210
Cerone AGotsman A(2018)Analysing Snapshot IsolationJournal of the ACM10.1145/315239665:2(1-41)Online publication date: 31-Jan-2018
https://dl.acm.org/doi/10.1145/3152396
Zhang WWang XJi SWei ZWang ZChen H(2018)Eunomia: Scaling Concurrent Index Structures Under Contention Using HTMIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2017.272955129:8(1837-1850)Online publication date: 1-Aug-2018
https://doi.org/10.1109/TPDS.2017.2729551
Wang XZhang WWang ZWei ZChen HZhao W(2017)EunomiaACM SIGPLAN Notices10.1145/3155284.301875252:8(385-399)Online publication date: 26-Jan-2017
https://dl.acm.org/doi/10.1145/3155284.3018752
Wang XZhang WWang ZWei ZChen HZhao WSarkar VRauchwerger L(2017)EunomiaProceedings of the 22nd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming10.1145/3018743.3018752(385-399)Online publication date: 26-Jan-2017
https://dl.acm.org/doi/10.1145/3018743.3018752
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