"A multilevel parasitic interconnect capacitance modeling and extraction ..."

Mankoo Lee (1998)

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DOI: 10.1109/4.663574

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type: Journal Article

metadata version: 2022-07-05

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Mankoo Lee:
A multilevel parasitic interconnect capacitance modeling and extraction for reliable VLSI on-chip clock delay evaluation. IEEE J. Solid State Circuits 33(4): 657-661 (1998)

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