Article

Iteration Space Tiling for Memory Hierarchies

Author:

Michael WolfeAuthors Info & Claims

Proceedings of the Third SIAM Conference on Parallel Processing for Scientific Computing

Pages 357 - 361

Published: 01 December 1987 Publication History

Abstract

No abstract available.

Cited By

View all

Patabandi THall MVerbrugge CLhot�k OShen X(2023)Efficiently Learning Locality Optimizations by Decomposing Transformation DomainsProceedings of the 32nd ACM SIGPLAN International Conference on Compiler Construction10.1145/3578360.3580272(37-49)Online publication date: 17-Feb-2023
https://dl.acm.org/doi/10.1145/3578360.3580272
Dally WTurakhia YHan S(2020)Domain-specific hardware acceleratorsCommunications of the ACM10.1145/336168263:7(48-57)Online publication date: 18-Jun-2020
https://dl.acm.org/doi/10.1145/3361682
Zinenko OVerdoolaege SReddy CShirako JGrosser TSarkar VCohen ADubach CXue J(2018)Modeling the conflicting demands of parallelism and Temporal/Spatial locality in affine schedulingProceedings of the 27th International Conference on Compiler Construction10.1145/3178372.3179507(3-13)Online publication date: 24-Feb-2018
https://dl.acm.org/doi/10.1145/3178372.3179507
Show More Cited By

Recommendations

More iteration space tiling
Supercomputing '89: Proceedings of the 1989 ACM/IEEE conference on Supercomputing

Subdividing the iteration space of a loop into blocks or tiles with a fixed maximum size has several advantages. Tiles become a natural candidate as the unit of work for parallel task scheduling. Synchronization between processors can be done between ...
On combining iteration space tiling with data space tiling for scratch-pad memory systems
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Most previous studies on tiling concentrate on iteration space only for cache-based memory systems. However, more and more real-time embedded systems are adopting Scratch-Pad Memories (SPMs) which emphasize on the management of data flow through data-...
Asymmetric memory hierarchies

A study is presented of some of the system implications of memory hierarchies in which the backing or secondary store has a very small read time, relative to both the time required for writing and to the read time of conventional backing storage ...

Comments

Information & Contributors

Information

Published In

Proceedings of the Third SIAM Conference on Parallel Processing for Scientific Computing

December 1987

386 pages

ISBN:0898712289

Editor:
Garry H. Rodrigue

Publisher

Society for Industrial and Applied Mathematics

United States

Publication History

Published: 01 December 1987

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

80
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 16 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Patabandi THall MVerbrugge CLhot�k OShen X(2023)Efficiently Learning Locality Optimizations by Decomposing Transformation DomainsProceedings of the 32nd ACM SIGPLAN International Conference on Compiler Construction10.1145/3578360.3580272(37-49)Online publication date: 17-Feb-2023
https://dl.acm.org/doi/10.1145/3578360.3580272
Dally WTurakhia YHan S(2020)Domain-specific hardware acceleratorsCommunications of the ACM10.1145/336168263:7(48-57)Online publication date: 18-Jun-2020
https://dl.acm.org/doi/10.1145/3361682
Zinenko OVerdoolaege SReddy CShirako JGrosser TSarkar VCohen ADubach CXue J(2018)Modeling the conflicting demands of parallelism and Temporal/Spatial locality in affine schedulingProceedings of the 27th International Conference on Compiler Construction10.1145/3178372.3179507(3-13)Online publication date: 24-Feb-2018
https://dl.acm.org/doi/10.1145/3178372.3179507
Trompouki MKosmidis L(2017)Optimisation opportunities and evaluation for GPGPU applications on low-end mobile GPUsProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130606(950-953)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130606
Prajapati NRanasinghe WRajopadhye SAndonov RDjidjev HGrosser T(2017)Simple, Accurate, Analytical Time Modeling and Optimal Tile Size Selection for GPGPU StencilsACM SIGPLAN Notices10.1145/3155284.301874452:8(163-177)Online publication date: 26-Jan-2017
https://dl.acm.org/doi/10.1145/3155284.3018744
Prajapati NRanasinghe WRajopadhye SAndonov RDjidjev HGrosser TSarkar VRauchwerger L(2017)Simple, Accurate, Analytical Time Modeling and Optimal Tile Size Selection for GPGPU StencilsProceedings of the 22nd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming10.1145/3018743.3018744(163-177)Online publication date: 26-Jan-2017
https://dl.acm.org/doi/10.1145/3018743.3018744
Caballero DRoyuela SFerrer RDuran AMartorell XBhuyan LChong FSarkar V(2015)Optimizing Overlapped Memory Accesses in User-directed VectorizationProceedings of the 29th ACM on International Conference on Supercomputing10.1145/2751205.2751224(393-404)Online publication date: 8-Jun-2015
https://dl.acm.org/doi/10.1145/2751205.2751224
Zhou XGarzar�n MPadua D(2015)Optimal Parallelogram Selection for Hierarchical TilingACM Transactions on Architecture and Code Optimization10.1145/268741411:4(1-23)Online publication date: 9-Jan-2015
https://dl.acm.org/doi/10.1145/2687414
Gonz�lez AAliagas CValero M(2014)A data cache with multiple caching strategies tuned to different types of localityACM International Conference on Supercomputing 25th Anniversary Volume10.1145/2591635.2667170(217-226)Online publication date: 10-Jun-2014
https://dl.acm.org/doi/10.1145/2591635.2667170
Ding WGuttman DKandemir MFlautner KWenisch TOzer EFerdman M(2014)Compiler Support for Optimizing Memory Bank-Level ParallelismProceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2014.34(571-582)Online publication date: 13-Dec-2014
https://dl.acm.org/doi/10.1109/MICRO.2014.34
Show More Cited By

View Options

View options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Abstract

Cited By

Recommendations

More iteration space tiling

On combining iteration space tiling with data space tiling for scratch-pad memory systems

Asymmetric memory hierarchies

Comments

Information

Published In

Publisher

Publication History

Qualifiers

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

Get Access

Login options

Full Access

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations