Article

Free access

A BIST approach to delay fault testing with reduced test length

Authors:

K. FuchsAuthors Info & Claims

EDTC '95: Proceedings of the 1995 European conference on Design and Test

Page 418

Published: 06 March 1995 Publication History

Abstract

A cost-effective built-in self testing (BIST) method for the detection of delay faults is presented. A multiple-input signature register (MISR) with a constant parallel input vector is used as a test pattern generator. To reduce the test length of the MISR, a two-step approach is proposed. First, deterministic delay test generation is employed to determine a set of two-pattern tests which detect all testable path delay faults. Second, a minimal number of constant MISR input vectors is calculated such that the state sequences generated by the MISR include the pre-determined test set. The second step is formulated as a set covering problem. As the number of MISR input vectors may be exponential in the number of stages of the MISR, their calculation and the set covering are performed implicitly with BDDs. Experimental results reveal that in almost all considered cases a maximum robust path delay fault coverage is obtained with less than 100 MISR input vectors.

References

[1]

[1] T. W. Williams, B. Underwood, and M. R. Mercer, "The Interdependence Between Delay-Optimization of Synthesized Networks and Testing," 28th ACM/IEEE Design Automation Conference DAC, pp. 87-92, 1991.

Digital Library

[2]

[2] K. Furuya and E. J. McCluskey, "Two-Pattern Test Capabilities of Autonomous TPG Circuits." IEEE International Test Conference, pp. 704-711, 1991.

Digital Library

[3]

[3] C. W. Starke, "Build-In Test for for CMOS Circuits," IEEE International Test Conference, pp. 309-314, 1984.

[4]

[4] C. A. Chen and S. K. Gupta, "BIST Test Pattern Generators for Stuck-Open and Delay Testing," European Design Automation Conference EDAC 1994, pp. 289-296, 1994.

[5]

[5] A. Vuksic and K. Fuchs, "A New BIST Approach for Delay Fault Testing," European Design Automation Conference EDAC 1994, pp. 284-288, 1994.

[6]

[6] G. L. Craig and C. R. Kime, "Pseudo-Exhaustive Adjacency Testinn: A BIST Approach for Stuck-Open Faults." IEEE International Test conference, pp. 126-137, 1985.

[7]

[7] G. L. Smith, "Model for Delay Faults Based upon Paths," IEEE International Test Conference, pp. 342-349, 1985.

[8]

[8] R. E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Transactions on Computers, vol. 35, no. 8, pp. 677-691, 1986.

Digital Library

[9]

[9] S. Lin and D. J. Costello, Error Control Coding: Fundamentals and Applications. Englewood Cliffs, N.J.: Prentice Hall, 1983.

Digital Library

[10]

[10] R. K. Brayton. G. D. Hachtel, C. T. McMullen, and A. L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis. Boston, MA: Kluwer Academic Publishers, 1984.

Digital Library

[11]

[11] S.- W. Jeong and F. Somenzi, "A New Algorithm for the Binate Covering Problem and its Application to the Minimization of Boolean Relations," IEEE/ACM International Conference on Computer-Aided Design ICCAD, pp. 417- 420, 1992.

Digital Library

[12]

[12] Y. Matsunaga, "MINT-An Exact Algorithm for Finding Minimum Test Set," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E76-A, no. 10, pp. 1652-1658, 1993.

[13]

[13] T. Kam, T. Villa, R. Brayton, and A. Sangiovanni-Vincentelli. "A Fully Implicit Algorithm for Exact State Minimization," 31th ACM/IEEE Besign Automation Conference DAC, 1994.

Digital Library

[14]

[14] O. Coudert and J. C. Madre, "A Unified Framework for the Formal Verification of Sequential Circuits," IEEE/ACM International Conference on Computer-Aided Design ICCAD , pp. 126-129 1990.

[15]

[15] K. Fuchs, F. Fink, and M. H. Schulz, "DYNAMITE: An Efficient Automatic Test Pattern Generation System for Path Delay Faults," IEEE Transactions on Computer-Aided Design , vol. 10, no. 10, pp. 1323-1335, 1991.

Digital Library

Cited By

Polian IBecker B(2004)Scalable Delay Fault BIST for Use with Low-Cost ATEJournal of Electronic Testing: Theory and Applications10.1023/B:JETT.0000023681.25483.5920:2(181-197)Online publication date: 1-Apr-2004
https://dl.acm.org/doi/10.1023/B%3AJETT.0000023681.25483.59
Li XCheung PFujiwara H(2000)LFSR-Based Deterministic TPG for Two-Pattern TestingJournal of Electronic Testing: Theory and Applications10.1023/A:100835631321216:5(419-426)Online publication date: 1-Oct-2000
https://dl.acm.org/doi/10.1023/A%3A1008356313212
Girard PLandrault CMoreda VPravossoudovitch S(1997)An optimized BIST test pattern generator for delay testingProceedings of the 15th IEEE VLSI Test Symposium10.5555/832297.836389Online publication date: 27-Apr-1997
https://dl.acm.org/doi/10.5555/832297.836389
Show More Cited By

A BIST approach to delay fault testing with reduced test length
1. Hardware

Recommendations

A new test pattern generation method for delay fault testing
VTS '96: Proceedings of the 14th IEEE VLSI Test Symposium

Importance of delay testing is growing especially for high speed circuits. As delay testing using automatic test equipment is expensive, built-in self-test is an alternative technique that can significantly reduce the cost of delay testing. In this ...
Accumulator-based BIST approach for stuck-open and delay fault testing
EDTC '95: Proceedings of the 1995 European conference on Design and Test

In this paper a novel accumulator-based Built-In Self Test (BIST) method for complete two-pattern test generation is presented. Complete two-pattern testing has been proposed for stuck-open and delay testing. The proposed scheme is very attractive for a ...
Chiba Scan Delay Fault Testing with Short Test Application Time

Delay fault testing using a scan design facilitating two-pattern testing, called Chiba scan testing, requires a long test application time (TAT) compared with well-known delay fault testing. This paper presents an improved Chiba scan testing with short ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

EDTC '95: Proceedings of the 1995 European conference on Design and Test

March 1995

556 pages

ISBN:0818670398

Copyright � Copyright (c) 1995 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society

United States

Publication History

Published: 06 March 1995

Check for updates

Author Tags

Qualifiers

Article

Conference

EDTC95

Sponsor:

SIGDA

EDTC95: European Design and Test Conference

March 6 - 9, 1995

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

4
Total Citations
View Citations
112
Total Downloads

Downloads (Last 12 months)23
Downloads (Last 6 weeks)10

Reflects downloads up to 17 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

Polian IBecker B(2004)Scalable Delay Fault BIST for Use with Low-Cost ATEJournal of Electronic Testing: Theory and Applications10.1023/B:JETT.0000023681.25483.5920:2(181-197)Online publication date: 1-Apr-2004
https://dl.acm.org/doi/10.1023/B%3AJETT.0000023681.25483.59
Li XCheung PFujiwara H(2000)LFSR-Based Deterministic TPG for Two-Pattern TestingJournal of Electronic Testing: Theory and Applications10.1023/A:100835631321216:5(419-426)Online publication date: 1-Oct-2000
https://dl.acm.org/doi/10.1023/A%3A1008356313212
Girard PLandrault CMoreda VPravossoudovitch S(1997)An optimized BIST test pattern generator for delay testingProceedings of the 15th IEEE VLSI Test Symposium10.5555/832297.836389Online publication date: 27-Apr-1997
https://dl.acm.org/doi/10.5555/832297.836389
Dufaza CZorian Y(1997)On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRsProceedings of the 1997 European conference on Design and Test10.5555/787260.787652Online publication date: 17-Mar-1997
https://dl.acm.org/doi/10.5555/787260.787652

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Table of Contents