research-article

Postsilicon Validation Methodology for Microprocessors

Author:

Hemant RotithorAuthors Info & Claims

IEEE Design & Test, Volume 17, Issue 4

Pages 77 - 88

https://doi.org/10.1109/54.895008

Published: 01 October 2000 Publication History

Abstract

This paper presents a systematic methodology for microarchitecture focused postsilicon system validation in the context of IA-32 Intel microprocessors. The need for a rigorous microarchitecture focused postsilicon validation is first established after analyzing presilicon and postsilicon validation techniques that CPU manufacturers have primarily used. The proposed methodology targets microarchitectural attributes that are prioritized based on their criticality for validation to identify corner cases. Several test templates cover all the critical attributes. Each template has an algorithm covering a subset of the attributes and automatically generates many tests by parameterizing around the corner case. Examples of application of the methodology are presented. Tests based on prioritized attributes help in narrowing the search of the huge validation space for complex logic-interaction type bugs in the early phase of silicon validation. The important issues in design and deployment of such tests are described and our solutions are discussed.

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Cited By

Baumann A(2017)Hardware is the new SoftwareProceedings of the 16th Workshop on Hot Topics in Operating Systems10.1145/3102980.3103002(132-137)Online publication date: 7-May-2017
https://dl.acm.org/doi/10.1145/3102980.3103002
Amit NTsafrir DSchuster AAyoub AShlomo EMiller EHand S(2015)Virtual CPU validationProceedings of the 25th Symposium on Operating Systems Principles10.1145/2815400.2815420(311-327)Online publication date: 4-Oct-2015
https://dl.acm.org/doi/10.1145/2815400.2815420
Abdel-Khalek RBertacco V(2014)Post-silicon platform for the functional diagnosis and debug of networks-on-chipACM Transactions on Embedded Computing Systems10.1145/256793613:3s(1-25)Online publication date: 28-Mar-2014
https://dl.acm.org/doi/10.1145/2567936
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Published In

cover image IEEE Design & Test

IEEE Design & Test Volume 17, Issue 4

October 2000

116 pages

ISSN:0740-7475

Issue’s Table of Contents

Copyright © Copyright © 2000 IEEE. All Rights Reserved.

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 October 2000

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Cited By

Baumann A(2017)Hardware is the new SoftwareProceedings of the 16th Workshop on Hot Topics in Operating Systems10.1145/3102980.3103002(132-137)Online publication date: 7-May-2017
https://dl.acm.org/doi/10.1145/3102980.3103002
Amit NTsafrir DSchuster AAyoub AShlomo EMiller EHand S(2015)Virtual CPU validationProceedings of the 25th Symposium on Operating Systems Principles10.1145/2815400.2815420(311-327)Online publication date: 4-Oct-2015
https://dl.acm.org/doi/10.1145/2815400.2815420
Abdel-Khalek RBertacco V(2014)Post-silicon platform for the functional diagnosis and debug of networks-on-chipACM Transactions on Embedded Computing Systems10.1145/256793613:3s(1-25)Online publication date: 28-Mar-2014
https://dl.acm.org/doi/10.1145/2567936
Foutris NGizopoulos DVera XGonzalez A(2013)Deconfigurable microprocessor architectures for silicon debug accelerationACM SIGARCH Computer Architecture News10.1145/2508148.248597641:3(631-642)Online publication date: 23-Jun-2013
https://dl.acm.org/doi/10.1145/2508148.2485976
Foutris NGizopoulos DVera XGonzalez AMendelson A(2013)Deconfigurable microprocessor architectures for silicon debug accelerationProceedings of the 40th Annual International Symposium on Computer Architecture10.1145/2485922.2485976(631-642)Online publication date: 23-Jun-2013
https://dl.acm.org/doi/10.1145/2485922.2485976
Foutris NGizopoulos DPsarakis MVera XGonzalez AGaluzzi CCarro LMoshovos APrvulovic M(2011)Accelerating microprocessor silicon validation by exposing ISA diversityProceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/2155620.2155666(386-397)Online publication date: 3-Dec-2011
https://dl.acm.org/doi/10.1145/2155620.2155666
Adir AGolubev MLanda SNahir AShurek GSokhin VZiv AStok LDutt NHassoun S(2011)ThreadmillProceedings of the 48th Design Automation Conference10.1145/2024724.2024916(860-865)Online publication date: 5-Jun-2011
https://dl.acm.org/doi/10.1145/2024724.2024916
Adir ANahir AShurek GZiv AMeissner CSchumann JStok LDutt NHassoun S(2011)Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processorProceedings of the 48th Design Automation Conference10.1145/2024724.2024856(569-574)Online publication date: 5-Jun-2011
https://dl.acm.org/doi/10.1145/2024724.2024856
Adir ANahir AZiv AMeissner CSchumann J(2010)Reaching coverage closure in post-silicon validationProceedings of the 6th international conference on Hardware and software: verification and testing10.5555/1987082.1987092(60-75)Online publication date: 4-Oct-2010
https://dl.acm.org/doi/10.5555/1987082.1987092
Bertacco VLin Y(2010)Post-silicon debugging for multi-core designsProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899776(255-258)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899776

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