Article

Exploiting Structural Duplication for Lifetime Reliability Enhancement

Authors:

Jayanth Srinivasan,

Sarita V. Adve,

Jude A. RiversAuthors Info & Claims

ISCA '05: Proceedings of the 32nd annual international symposium on Computer Architecture

Pages 520 - 531

https://doi.org/10.1109/ISCA.2005.28

Published: 01 May 2005 Publication History

Abstract

Increased power densities (and resultant temperatures) and other effects of device scaling are predicted to cause significant lifetime reliability problems in the near future. In this paper, we study two techniques that leverage microarchitectural structural redundancy for lifetime reliability enhancement. First, in structural duplication (SD), redundant microarchitectural structures are added to the processor and designated as spares. Spare structures can be turned on when the original structure fails, increasing the processor�s lifetime. Second, graceful performance degradation (GPD) is a technique which exploits existing microarchitectural redundancy for reliability. Redundant structures that fail are shut down while still maintaining functionality, thereby increasing the processor�s lifetime, but at a lower performance. Our analysis shows that exploiting structural redundancy can provide significant reliability benefits, and we present guidelines for efficient usage of these techniques by identifying situations where each is more beneficial. We show that GPD is the superior technique when only limited performance or cost resources can be sacrificed for reliability. Specifically, on average for our systems and applications,GPD increased processor reliability to 1.42 times the base value for less than a 5% loss in performance. On the other hand, for systems where reliability is more important than performance or cost, SD is more beneficial. SD increases reliability to 3.17 times the base value for 2.25 times the base cost, for our applications. Finally, a combination of the two techniques (SD+GPD) provides the highest reliability benefit.

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Ma CMahajan AMeyer B(2017)Multi-armed bandits for efficient lifetime estimation in MPSoC designProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130739(1544-1549)Online publication date: 27-Mar-2017
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Psychou GRodopoulos DSabry MGemmeke TAtienza DNoll TCatthoor F(2017)Classification of Resilience Techniques Against Functional Errors at Higher Abstraction Layers of Digital SystemsACM Computing Surveys10.1145/309269950:4(1-38)Online publication date: 4-Oct-2017
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Balboni MBertozzi DSonntag SGarc�a Carrasco JAbellan Miguel JGritschneder D(2017)Transparent lifetime built-in self-testing of networks-on-chip through the selective non-concurrent testing of their communication channelsProceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems10.1145/3073763.3073765(12-17)Online publication date: 25-Jan-2017
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cover image ACM Conferences

ISCA '05: Proceedings of the 32nd annual international symposium on Computer Architecture

June 2005

541 pages

ISBN:076952270X

ACM SIGARCH Computer Architecture News Volume 33, Issue 2
ISCA 2005
May 2005
531 pages
ISSN:0163-5964
DOI:10.1145/1080695
Issue’s Table of Contents

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SIGARCH: ACM Special Interest Group on Computer Architecture

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IEEE Computer Society

United States

Publication History

Published: 01 May 2005

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ISCA05: The 32nd Annual International Symposium on Computer Architecture 2005

June 4 - 8, 2005

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ISCA '05 Paper Acceptance Rate 45 of 194 submissions, 23%;

Overall Acceptance Rate 543 of 3,203 submissions, 17%

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Cited By

Ma CMahajan AMeyer B(2017)Multi-armed bandits for efficient lifetime estimation in MPSoC designProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130739(1544-1549)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130739
Psychou GRodopoulos DSabry MGemmeke TAtienza DNoll TCatthoor F(2017)Classification of Resilience Techniques Against Functional Errors at Higher Abstraction Layers of Digital SystemsACM Computing Surveys10.1145/309269950:4(1-38)Online publication date: 4-Oct-2017
https://dl.acm.org/doi/10.1145/3092699
Balboni MBertozzi DSonntag SGarc�a Carrasco JAbellan Miguel JGritschneder D(2017)Transparent lifetime built-in self-testing of networks-on-chip through the selective non-concurrent testing of their communication channelsProceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems10.1145/3073763.3073765(12-17)Online publication date: 25-Jan-2017
https://dl.acm.org/doi/10.1145/3073763.3073765
Ashraf RKhoshavi NAlzahrani ADeMara RKiamehr STahoori MPalermo GFeo JTumeo AFranke H(2016)Area-energy tradeoffs of logic wear-leveling for BTI-induced agingProceedings of the ACM International Conference on Computing Frontiers10.1145/2903150.2903171(37-44)Online publication date: 16-May-2016
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Arunachalam SChantem TDick RHu XNicolescu GGerstlauer A(2015)An online wear state monitoring methodology for off-the-shelf embedded processorsProceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis10.5555/2830840.2830853(114-123)Online publication date: 4-Oct-2015
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Hong HLim JLim HKang S(2015)Lifetime Reliability Enhancement of MicroprocessorsACM Computing Surveys10.1145/278598848:1(1-25)Online publication date: 29-Sep-2015
https://dl.acm.org/doi/10.1145/2785988
Pan ARodrigues RKundu S(2015)A Hardware Framework for Yield and Reliability Enhancement in Chip MultiprocessorsACM Transactions on Embedded Computing Systems10.1145/262968814:1(1-26)Online publication date: 21-Jan-2015
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Yalcin GErgin OIslek EUnsal OCristal A(2014)Exploiting Existing Comparators for Fine-Grained Low-Cost Error DetectionACM Transactions on Architecture and Code Optimization10.1145/265634111:3(1-24)Online publication date: 27-Oct-2014
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Sun JLysecky RShankar KKodi ALouri ARoveda J(2014)Workload assignment considering NBTI degradation in multicore systemsACM Journal on Emerging Technologies in Computing Systems10.1145/253912410:1(1-22)Online publication date: 13-Jan-2014
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Meyer BHartman AThomas D(2014)Cost-effective lifetime and yield optimization for NoC-based MPSoCsACM Transactions on Design Automation of Electronic Systems10.1145/253557519:2(1-33)Online publication date: 28-Mar-2014
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