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Area-energy tradeoffs of logic wear-leveling for BTI-induced aging

Authors:

Mehdi B. TahooriAuthors Info & Claims

CF '16: Proceedings of the ACM International Conference on Computing Frontiers

Pages 37 - 44

https://doi.org/10.1145/2903150.2903171

Published: 16 May 2016 Publication History

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Abstract

Ensuring operational reliability in the presence of Bias Temperature Instability (BTI) effects often results in a compromise either in the form of lower performance and/or higher energy-consumption. This is due to the performance degradation over time caused by BTI effects which needs to be compensated through frequency, voltage, or area margining to meet the circuit's timing specification till end of operational lifetime. In this paper, a circuit-level approach referred to as Logic-Wear-Leveling (LWL) utilizes Dark-Silicon to mitigate BTI effects in logic datapaths. LWL introduces fine-grained spatial redundancy in timing vulnerable logic components, and leverages it at runtime to enable post-Silicon adaptability. The activation interval of redundant datapaths allows for controlled stress and recovery phases. This produces a wear-leveling effect which helps to reduce the BTI induced performance degradation over time, which in turn helps to reduce the design margins. This approach demonstrates a significant reduction in energy consumption of up to 31.98% at 10 years as compared to conventional voltage guardbanding approach. The benefit of energy reduction is also assessed against the area overheads of spatial redundancy.

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Cited By

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Sobas JMarc F(2023)Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGAMicromachines10.3390/mi1501001915:1(19)Online publication date: 22-Dec-2023
https://doi.org/10.3390/mi15010019
Listl AMueller-Gritschneder DSchlichtmann U(2019)MAGIC: A Wear-leveling Circuitry to Mitigate Aging Effects in Sense Amplifiers of SRAMs2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)10.1109/NEWCAS44328.2019.8961241(1-4)Online publication date: Jun-2019
https://doi.org/10.1109/NEWCAS44328.2019.8961241
Guo XStan MGuo XStan M(2019)Introduction to WearoutCircadian Rhythms for Future Resilient Electronic Systems10.1007/978-3-030-20051-0_1(3-14)Online publication date: 13-Jun-2019
https://doi.org/10.1007/978-3-030-20051-0_1
Show More Cited By

Index Terms

Area-energy tradeoffs of logic wear-leveling for BTI-induced aging
1. Hardware
  1. Robustness
    1. Hardware reliability
      1. Aging of circuits and systems

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Reviews

Reviewer: Xinfei Guo

As technology nodes are scaled down into the nanometer level, the reliability of the devices for an electronic chip becomes critical. Among various reliability threats, aging is one of the most prominent, as it introduces gradual parameter and metric (like performance) degradation, and eventually failures. Bias temperature instability (BTI) is a dominant aging issue that shifts the threshold voltage of the transistors when under voltage stress; when the voltage is removed, there is a slow recovery process. The longer the recovery process, the less cumulative aging will be. Various previous solutions aim to tune certain metrics to deal with aging, such as balancing the signal probability or adding guardband. But none of the solutions are perfect; additional overhead will still be introduced. One such tradeoff is usually energy and aging; by fixing aging issues, more energy needs to be consumed. In this paper, Ashraf et al. propose a novel idea of dealing with aging at the circuit level by replicating the critical paths or near-critical paths. By taking advantage of such redundancy and switching between the replicated paths, the overall aging can be leveraged, thus the guardband can be reduced. Although the proposed solution will affect the area overhead, the paper presents a detailed evaluation and shows the area overhead is minimal if only replicating several critical path candidates. A design flow that can be adapted to the existing electronic design automation (EDA) tools is also proposed. The reported experimental results show that the guardband is significantly reduced; this is translated directly to the energy savings (about 31.98 percent). The paper also considers the area and energy tradeoff, and the conclusion is that the approach achieves very low area overhead while getting huge energy savings. This paper shows a circuit-level implementation of coping with reliability by utilizing redundancy. It presents a very comprehensive analysis of various tradeoffs. While further study can be done, such as fanout, leakage issues and the added design efforts are some aspects that can still be addressed. Also, if dark silicon can be used together with the proposed circuit solution, there will be more improvements. Online Computing Reviews Service

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Published In

CF '16: Proceedings of the ACM International Conference on Computing Frontiers

May 2016

487 pages

ISBN:9781450341288

DOI:10.1145/2903150

General Chairs:
Gianluca Palermo
Politecnico di Milano, IT
,
John Feo
Pacific Northwest National Laboratory and Northwest Institute for Advanced Computing
,
Program Chairs:
Antonino Tumeo
Pacific Northwest National Laboratory, USA
,
Hubertus Franke
New York University and IBM Research, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 16 May 2016

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Micron Foundation
ACM
Politecnico di Milano
SIGMICRO
IBM

CF'16: Computing Frontiers Conference

May 16 - 19, 2016

Como, Italy

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CF '16 Paper Acceptance Rate 30 of 94 submissions, 32%;

Overall Acceptance Rate 273 of 785 submissions, 35%

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Cited By

View all

Sobas JMarc F(2023)Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGAMicromachines10.3390/mi1501001915:1(19)Online publication date: 22-Dec-2023
https://doi.org/10.3390/mi15010019
Listl AMueller-Gritschneder DSchlichtmann U(2019)MAGIC: A Wear-leveling Circuitry to Mitigate Aging Effects in Sense Amplifiers of SRAMs2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)10.1109/NEWCAS44328.2019.8961241(1-4)Online publication date: Jun-2019
https://doi.org/10.1109/NEWCAS44328.2019.8961241
Guo XStan MGuo XStan M(2019)Introduction to WearoutCircadian Rhythms for Future Resilient Electronic Systems10.1007/978-3-030-20051-0_1(3-14)Online publication date: 13-Jun-2019
https://doi.org/10.1007/978-3-030-20051-0_1
Khoshavi NAshraf RDeMara RKiamehr SOboril FTahoori M(2017)Contemporary CMOS aging mitigation techniquesIntegration, the VLSI Journal10.1016/j.vlsi.2017.03.01359:C(10-22)Online publication date: 1-Sep-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2017.03.013

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Modeling and minimization of PMOS NBTI effect for robust nanometer design

TG-based technique for NBTI degradation and leakage optimization

On-chip aging sensor circuits for reliable nanometer MOSFET digital circuits

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Recommendations

Modeling and minimization of PMOS NBTI effect for robust nanometer design

TG-based technique for NBTI degradation and leakage optimization

On-chip aging sensor circuits for reliable nanometer MOSFET digital circuits

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