Article

A Mechanism for Online Diagnosis of Hard Faults in Microprocessors

Authors:

Daniel J. Sorin,

Sule OzevAuthors Info & Claims

MICRO 38: Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture

Pages 197 - 208

https://doi.org/10.1109/MICRO.2005.8

Published: 12 November 2005 Publication History

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Abstract

We develop a microprocessor design that tolerates hard faults, including fabrication defects and in-field faults, by leveraging existing microprocessor redundancy. To do this, we must: detect and correct errors, diagnose hard faults at the field deconfigurable unit (FDU) granularity, and deconfigure FDUs with hard faults. In our reliable microprocessor design, we use DIVA dynamic verification to detect and correct errors. Our new scheme for diagnosing hard faults tracks instructions' core structure occupancy from decode until commit. If a DIVA checker detects an error in an instruction, it increments a small saturating error counter for every FDU used by that instruction, including that DIVA checker. A hard fault in an FDU quickly leads to an above-threshold error counter for that FDU and thus diagnoses the fault. For deconfiguration, we use previously developed schemes for functional units and buffers, and we present a scheme for deconfiguring DIVA checkers. Experimental results show that our reliable microprocessor quickly and accurately diagnoses each hard fault that is injected and continues to function, albeit with somewhat degraded performance.

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Liu HSilvestro SZhang XHuang JLiu T(2020)WATCHER: in-situ failure diagnosisProceedings of the ACM on Programming Languages10.1145/34282114:OOPSLA(1-27)Online publication date: 13-Nov-2020
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Index Terms

A Mechanism for Online Diagnosis of Hard Faults in Microprocessors
1. Hardware

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Published In

cover image ACM Conferences

MICRO 38: Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture

November 2005

350 pages

ISBN:0769524400

Sponsors

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

IEEE Computer Society

United States

Publication History

Published: 12 November 2005

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Micro-38

Sponsor:

SIGMICRO

Micro-38: The 38th Annual IEEE/ACM International Symposium on Microarchitecture

November 12 - 16, 2005

Barcelona, Spain

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MICRO 38 Paper Acceptance Rate 29 of 147 submissions, 20%;

Overall Acceptance Rate 484 of 2,242 submissions, 22%

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MICRO '24

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sigmicro

57th Annual IEEE/ACM International Symposium on Microarchitecture

November 2 - 6, 2024

Austin , TX , USA

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Cited By

Liu HSilvestro SZhang XHuang JLiu T(2020)WATCHER: in-situ failure diagnosisProceedings of the ACM on Programming Languages10.1145/34282114:OOPSLA(1-27)Online publication date: 13-Nov-2020
https://dl.acm.org/doi/10.1145/3428211
Psychou GRodopoulos DSabry MGemmeke TAtienza DNoll TCatthoor F(2017)Classification of Resilience Techniques Against Functional Errors at Higher Abstraction Layers of Digital SystemsACM Computing Surveys10.1145/309269950:4(1-38)Online publication date: 4-Oct-2017
https://dl.acm.org/doi/10.1145/3092699
Pan ARodrigues RKundu S(2015)A Hardware Framework for Yield and Reliability Enhancement in Chip MultiprocessorsACM Transactions on Embedded Computing Systems10.1145/262968814:1(1-26)Online publication date: 21-Jan-2015
https://dl.acm.org/doi/10.1145/2629688
Dweik WAnnavaram MDubois MFettweis GNebel W(2014)Reliability-aware exceptionsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616731(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616731
Yalcin GErgin OIslek EUnsal OCristal A(2014)Exploiting Existing Comparators for Fine-Grained Low-Cost Error DetectionACM Transactions on Architecture and Code Optimization10.1145/265634111:3(1-24)Online publication date: 27-Oct-2014
https://dl.acm.org/doi/10.1145/2656341
Rodrigues RAnnamalai AKundu S(2014)A low-power instruction replay mechanism for design of resilient microprocessorsACM Transactions on Embedded Computing Systems10.1145/256003413:4(1-23)Online publication date: 10-Mar-2014
https://dl.acm.org/doi/10.1145/2560034
Foutris NGizopoulos DVera XGonzalez A(2013)Deconfigurable microprocessor architectures for silicon debug accelerationACM SIGARCH Computer Architecture News10.1145/2508148.248597641:3(631-642)Online publication date: 23-Jun-2013
https://dl.acm.org/doi/10.1145/2508148.2485976
Foutris NGizopoulos DVera XGonzalez AMendelson A(2013)Deconfigurable microprocessor architectures for silicon debug accelerationProceedings of the 40th Annual International Symposium on Computer Architecture10.1145/2485922.2485976(631-642)Online publication date: 23-Jun-2013
https://dl.acm.org/doi/10.1145/2485922.2485976
Khudia DWright GMahlke S(2012)Efficient soft error protection for commodity embedded microprocessors using profile informationACM SIGPLAN Notices10.1145/2345141.224843347:5(99-108)Online publication date: 12-Jun-2012
https://dl.acm.org/doi/10.1145/2345141.2248433
Khudia DWright GMahlke SWilhelm RFalk HYi W(2012)Efficient soft error protection for commodity embedded microprocessors using profile informationProceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems10.1145/2248418.2248433(99-108)Online publication date: 12-Jun-2012
https://dl.acm.org/doi/10.1145/2248418.2248433
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